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    Selective post-doping of gate structures by means of selective oxide growth
    5.
    发明授权
    Selective post-doping of gate structures by means of selective oxide growth 失效
    通过选择性氧化物生长选择性地掺杂栅极结构

    公开(公告)号：US07288814B2

    公开(公告)日：2007-10-30

    申请号：US11268100

    申请日：2005-11-07

    申请人： Anthony I. Chou ,  Toshiharu Furukawa ,  Steven J. Holmes

    发明人： Anthony I. Chou ,  Toshiharu Furukawa ,  Steven J. Holmes

    IPC分类号： H01L29/94

    CPC分类号： H01L29/6659 ,  H01L21/02131 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/266 ,  H01L21/316 ,  H01L21/31612 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833

    摘要： A method for doping a polysilicon gate conductor, without implanting the substrate in a manner that would effect source/drain formation is provided. The inventive method comprises forming at least one polysilicon gate region atop a substrate; forming oxide seed spacers abutting the polysilicon gate; forming source/drain oxide spacers selectively deposited on the oxide seed spacers by liquid phase deposition, and implanting at least one polysilicon gate region, wherein the source/drain oxide spacers protect an underlying portion of the substrate. Multiple gate regions may be processed on a single substrate using conventional patterning. A block-mask provided by patterned photoresist can be used prior to implantation to pre-select the substrate area for gate conductor doping with one dopant type.

    摘要翻译： 提供了掺杂多晶硅栅极导体而不以将影响源极/漏极形成的方式植入衬底的方法。 本发明的方法包括在基板顶上形成至少一个多晶硅栅极区域; 形成邻接所述多晶硅栅极的氧化物种子间隔物; 通过液相沉积选择性地沉积在氧化物种间隔物上的源极/漏极氧化物间隔区，以及注入至少一个多晶硅栅极区域，其中源极/漏极氧化物间隔物保护衬底的下面部分。 可以使用常规图案化在单个基板上处理多个栅极区域。 在植入之前可以使用由图案化的光致抗蚀剂提供的块掩模，以预先选择用于掺杂一种掺杂剂类型的栅极导体的衬底区域。

    POLYGRAIN ENGINEERING BY ADDING IMPURITIES IN THE GAS PHASE DURING CHEMICAL VAPOR DEPOSITION OF POLYSILICON
    8.
    发明申请
    POLYGRAIN ENGINEERING BY ADDING IMPURITIES IN THE GAS PHASE DURING CHEMICAL VAPOR DEPOSITION OF POLYSILICON 审中-公开
    通过在多晶硅化学气相沉积期间在气相中添加污染物进行聚合工程

    公开(公告)号：US20090269926A1

    公开(公告)日：2009-10-29

    申请号：US12110594

    申请日：2008-04-28

    申请人： Abhishek Dube ,  Ashima B. Chakravarti ,  Anthony I. Chou ,  Wei He ,  Dominic J. Schepis

    发明人： Abhishek Dube ,  Ashima B. Chakravarti ,  Anthony I. Chou ,  Wei He ,  Dominic J. Schepis

    IPC分类号： H01L21/44

    CPC分类号： H01L21/28035 ,  H01L29/4925

    摘要： A method of forming at least one gate conductor of a complementary metal oxide semiconductor performs a chemical vapor deposition process of polysilicon over a surface where a polysilicon gate is to be located. This deposition can be performed through a mask to form gate structures directly, or a later patterning process can pattern the polysilicon into gate structures. During the chemical vapor deposition process, the method adds impurities in the chemical vapor deposition process to optimize the grain size of the polysilicon according to a number of different methods.

    摘要翻译： 形成互补金属氧化物半导体的至少一个栅极导体的方法在多晶硅栅极位于的表面上进行多晶硅的化学气相沉积处理。 该沉积可以通过掩模进行直接形成栅极结构，或者后来的图案化工艺可以将多晶硅图案化成栅极结构。 在化学气相沉积过程中，该方法根据多种不同的方法在化学气相沉积工艺中添加杂质以优化多晶硅的晶粒尺寸。

    SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURES INCLUDING GRADIENT NITRIDED BURIED OXIDE (BOX)
    9.
    发明申请
    SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURES INCLUDING GRADIENT NITRIDED BURIED OXIDE (BOX) 有权
    半导体绝缘体（SOI）结构，包括梯度氮化氧化物（BOX）

    公开(公告)号：US20120049317A1

    公开(公告)日：2012-03-01

    申请号：US13290634

    申请日：2011-11-07

    申请人： Anthony I. Chou ,  Toshiharu Furukawa ,  Wilfried Haensch ,  Zhibin Ren ,  Dinkar V. Singh ,  Jeffrey W. Sleight

    发明人： Anthony I. Chou ,  Toshiharu Furukawa ,  Wilfried Haensch ,  Zhibin Ren ,  Dinkar V. Singh ,  Jeffrey W. Sleight

    IPC分类号： H01L29/12

    CPC分类号： H01L29/78603 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.

    摘要翻译： 绝缘体上半导体结构包括插入在基底半导体衬底和表面半导体层之间的掩埋电介质层。 掩埋介电层包括氧化物材料，其包括氮化物梯度，其在掩埋介电层的界面处与基底半导体衬底和表面半导体层中的至少一个相接触。 掩埋介质层与基底半导体衬底和表面半导体层中的至少一个的界面是突然的，提供小于约5原子层厚度的转变，并且具有小于约10埃的RMS界面粗糙度。 包含不含氮的氧化物介电材料的第二电介质层可位于掩埋介电层和表面半导体层之间。

    Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX)
    10.
    发明授权
    Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX) 有权
    绝缘体上半导体（SOI）结构包括梯度氮化掩埋氧化物（BOX）

    公开(公告)号：US07396776B2

    公开(公告)日：2008-07-08

    申请号：US11483901

    申请日：2006-07-10

    申请人： Anthony I. Chou ,  Toshiharu Furukawa ,  Wilfried Haensch ,  Zhibin Ren ,  Dinkar V. Singh ,  Jeffrey W. Sleight

    发明人： Anthony I. Chou ,  Toshiharu Furukawa ,  Wilfried Haensch ,  Zhibin Ren ,  Dinkar V. Singh ,  Jeffrey W. Sleight

    IPC分类号： H01L21/00

    CPC分类号： H01L29/78603 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.

    摘要翻译： 绝缘体上半导体结构包括插入在基底半导体衬底和表面半导体层之间的掩埋电介质层。 掩埋介电层包括氧化物材料，其包括氮化物梯度，其在掩埋介电层的界面处与基底半导体衬底和表面半导体层中的至少一个相接触。 掩埋介质层与基底半导体衬底和表面半导体层中的至少一个的界面是突然的，提供小于约5原子层厚度的转变，并且具有小于约10埃的RMS界面粗糙度。 包含不含氮的氧化物介电材料的第二电介质层可位于掩埋介电层和表面半导体层之间。