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1.发明申请JUNCTION FIELD EFFECT TRANSISTORS IN GERMANIUM AND SILICON-GERMANIUM ALLOYS AND METHOD FOR MAKING AND USING 审中-公开锗和锗 - 锗合金中的结型场效应晶体管及其制造和使用方法公开(公告)号：US20080272394A1
公开(公告)日：2008-11-06
申请号：US11870212
申请日：2007-10-10
IPC分类号： H01L29/808 , H01L21/337 , H01L29/00
CPC分类号： H01L29/66901 , H01L21/2257 , H01L21/761 , H01L21/76224 , H01L29/0653 , H01L29/0843 , H01L29/1066 , H01L29/1075 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/45 , H01L29/808 , H01L29/8086
摘要： Junction field effect transistors (JFET) formed in substrates containing germanium. JFETs having polycrystalline semiconductor surface contacts with self-aligned silicide formed thereon and self-aligned source, drain and gate regions formed by thermal drive-in of impurities from surface contacts into the substrate, and implanted link regions. Others have a polycrystalline semiconductor gate surface contact and metal back gate, source and drain contacts and a metal surface contact to the gate surface contact with implanted source and drains and a self-aligned gate region. JFETs having a polycrystalline semiconductor gate surface contact and metal back gate, source and drain contacts and a metal surface contact to the gate surface contact with implanted source and drains and a self-aligned gate region and silicide formed on the top of the source, drain and back gate contacts and on top of the gate polycrystalline semiconductor gate contact to which the metal surface contacts make electrical contact.
摘要翻译： 在包含锗的衬底中形成的结型场效应晶体管（JFET）。 具有形成在其上的自对准硅化物的多晶半导体表面接触的JFET和通过从表面接触进入衬底的杂质的热驱动形成的自对准源极，漏极和栅极区域以及植入的连接区域。 其他具有多晶半导体栅极表面接触和金属后栅极，源极和漏极接触以及与栅极表面接触的金属表面接触与注入源和漏极以及自对准栅极区域。 具有多晶半导体栅极表面接触和金属背栅极，源极和漏极接触以及与栅极表面的金属表面接触的JFET与注入源和漏极接触，并且形成在源极，漏极的顶部上的自对准栅极区域和硅化物 和后栅极触点，并且在栅极多晶半导体栅极触点的顶部上，金属表面触点与触点形成电接触。
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2.发明授权公开(公告)号：US08530286B2
公开(公告)日：2013-09-10
申请号：US12971884
申请日：2010-12-17
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823878 , H01L21/823892 , H01L29/7833
摘要： A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.
摘要翻译： 其制造的结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有降低的sigmaVT，并且可以允许在沟道区中具有掺杂剂的FET的阈值电压VT被设置 更准确地说 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。 半导体结构包括模拟器件和数字器件，每个器件和数字器件均具有外延沟道层，其中单个栅极氧化层位于数字器件的NMOS和PMOS晶体管元件的外延沟道层上，并且双栅极和三栅极氧化层之一是 在模拟器件的NMOS和PMOS晶体管元件的外延沟道层上。
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公开(公告)号：US20110121404A1
公开(公告)日：2011-05-26
申请号：US12895813
申请日：2010-09-30
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/1083 , H01L21/823412 , H01L21/82345 , H01L21/823493 , H01L27/088 , H01L27/092 , H01L29/0847 , H01L29/1033 , H01L29/1045 , H01L29/36 , H01L29/66537 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7836
摘要： An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.
摘要翻译： 具有穿通抑制的高级晶体管包括具有长度为Lg的阱，阱掺杂以具有掺杂剂的第一浓度，以及位于栅极下方并具有第二掺杂浓度的屏蔽区域。 掺杂剂的第二浓度可以大于每立方厘米5×1018个掺杂剂原子。 在筛选区域和井之间的栅极下方设置有至少一个穿孔抑制区域。 穿通抑制区域具有在第一浓度和第二浓度掺杂剂之间的掺杂剂的第三浓度。 可以将偏置电压施加到阱区域以调整晶体管的阈值电压。
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4.发明申请公开(公告)号：US20090137088A1
公开(公告)日：2009-05-28
申请号：US12362920
申请日：2009-01-30
IPC分类号： H01L21/337
CPC分类号： H01L29/1058 , H01L29/66901 , H01L29/808
摘要： A junction field effect transistor comprises a semiconductor substrate, a source region formed in the substrate, a drain region formed in the substrate and spaced apart from the source region, and a gate region formed in the substrate. The transistor further comprises a first channel region formed in the substrate and spaced apart from the gate region, and a second channel region formed in the substrate and between the first channel region and the gate region. The second channel region has a higher concentration of doped impurities than the first channel region.
摘要翻译： 结型场效应晶体管包括半导体衬底，形成在衬底中的源极区，形成在衬底中并与源极区隔开的漏极区和形成在衬底中的栅极区。 晶体管还包括形成在衬底中并与栅极区隔开的第一沟道区，以及形成在衬底中以及在第一沟道区和栅极区之间的第二沟道区。 第二沟道区具有比第一沟道区更高的掺杂杂质浓度。
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5.发明申请公开(公告)号：US20080272409A1
公开(公告)日：2008-11-06
申请号：US11744113
申请日：2007-05-03
IPC分类号： H01L21/337 , H01L29/80
CPC分类号： H01L29/1058 , H01L29/66901 , H01L29/808
摘要： A junction field effect transistor comprises a semiconductor substrate, a source region formed in the substrate, a drain region formed in the substrate and spaced apart from the source region, and a gate region formed in the substrate. The transistor further comprises a first channel region formed in the substrate and spaced apart from the gate region, and a second channel region formed in the substrate and between the first channel region and the gate region. The second channel region has a higher concentration of doped impurities than the first channel region.
摘要翻译： 结型场效应晶体管包括半导体衬底，形成在衬底中的源极区，形成在衬底中并与源极区隔开的漏极区和形成在衬底中的栅极区。 晶体管还包括形成在衬底中并与栅极区隔开的第一沟道区，以及形成在衬底中以及在第一沟道区和栅极区之间的第二沟道区。 第二沟道区具有比第一沟道区更高的掺杂杂质浓度。
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公开(公告)号：US20130181298A1
公开(公告)日：2013-07-18
申请号：US13787073
申请日：2013-03-06
申请人： Lucian Shifren , Pushkar Ranade , Paul E. Gregory , Sachin R. Sonkusale , Weimin Zhang , Scott E. Thompson
发明人： Lucian Shifren , Pushkar Ranade , Paul E. Gregory , Sachin R. Sonkusale , Weimin Zhang , Scott E. Thompson
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L29/1083 , H01L21/823412 , H01L21/82345 , H01L21/823493 , H01L27/088 , H01L27/092 , H01L29/0847 , H01L29/1033 , H01L29/1045 , H01L29/36 , H01L29/66537 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7836
摘要： An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.
摘要翻译： 具有穿通抑制的高级晶体管包括具有长度为Lg的阱，阱掺杂以具有掺杂剂的第一浓度，以及位于栅极下方并具有第二掺杂浓度的屏蔽区域。 掺杂剂的第二浓度可以大于每立方厘米5×1018个掺杂剂原子。 在筛选区域和井之间的栅极下方设置有至少一个穿孔抑制区域。 穿通抑制区域具有在第一浓度和第二浓度掺杂剂之间的掺杂剂的第三浓度。 可以将偏置电压施加到阱区域以调整晶体管的阈值电压。
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公开(公告)号：US08421162B2
公开(公告)日：2013-04-16
申请号：US12895813
申请日：2010-09-30
申请人： Lucian Shifren , Pushkar Ranade , Paul E. Gregory , Sachin R. Sonkusale , Weimin Zhang , Scott E. Thompson
发明人： Lucian Shifren , Pushkar Ranade , Paul E. Gregory , Sachin R. Sonkusale , Weimin Zhang , Scott E. Thompson
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/1083 , H01L21/823412 , H01L21/82345 , H01L21/823493 , H01L27/088 , H01L27/092 , H01L29/0847 , H01L29/1033 , H01L29/1045 , H01L29/36 , H01L29/66537 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7836
摘要： An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.
摘要翻译： 具有穿通抑制的高级晶体管包括具有长度为Lg的阱，阱掺杂以具有掺杂剂的第一浓度，以及位于栅极下方并具有第二掺杂浓度的屏蔽区域。 掺杂剂的第二浓度可以大于每立方厘米5×1018个掺杂剂原子。 在筛选区域和井之间的栅极下方设置有至少一个穿孔抑制区域。 穿通抑制区域具有在第一浓度和第二浓度掺杂剂之间的掺杂剂的第三浓度。 可以将偏置电压施加到阱区域以调整晶体管的阈值电压。
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8.发明申请公开(公告)号：US20110248352A1
公开(公告)日：2011-10-13
申请号：US12971884
申请日：2010-12-17
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823878 , H01L21/823892 , H01L29/7833
摘要： A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.
摘要翻译： 其制造的结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有减小的VT，并且可以允许在沟道区中具有掺杂剂的FET的阈值电压VT 更精确地设置。 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。 半导体结构包括模拟器件和数字器件，每个器件和数字器件均具有外延沟道层，其中单个栅极氧化层位于数字器件的NMOS和PMOS晶体管元件的外延沟道层上，并且双栅极和三栅极氧化层之一是 在模拟器件的NMOS和PMOS晶体管元件的外延沟道层上。
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公开(公告)号：US08569128B2
公开(公告)日：2013-10-29
申请号：US12960266
申请日：2010-12-03
IPC分类号： H01L21/823842 , H01L21/823807
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823842 , H01L27/0922
摘要： A semiconductor structure includes a first PMOS transistor element having a gate region with a first gate metal associated with a PMOS work function and a first NMOS transistor element having a gate region with a second metal associated with a NMOS work function. The first PMOS transistor element and the first NMOS transistor element form a first CMOS device. The semiconductor structure also includes a second PMOS transistor that is formed in part by concurrent deposition with the first NMOS transistor element of the second metal associated with a NMOS work function to form a second CMOS device with different operating characteristics than the first CMOS device.
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公开(公告)号：US08563384B2
公开(公告)日：2013-10-22
申请号：US13770313
申请日：2013-02-19
IPC分类号： H01L21/336 , H01L21/70 , H01L29/02
CPC分类号： H01L29/7816 , H01L27/085 , H01L27/088 , H01L29/105 , H01L29/1083 , H01L29/165 , H01L29/66537 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7835 , H01L29/7848
摘要： A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3′, or alternatively, less than one-quarter the dopant concentration of the source and the drain.
摘要翻译： 具有改进性能的平面晶体管在半导体衬底上具有源极和漏极，其包括在源极和漏极之间延伸的基本上未掺杂的沟道。 栅极位于衬底上的基本上未掺杂的沟道上。 注入源极/漏极延伸部接触源极和漏极，注入源极/漏极延伸部的掺杂剂浓度小于约1×1019原子/ cm3'，或者可选地，小于源极的掺杂剂浓度的四分之一，以及 排水。
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