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公开(公告)号：US07690024B2
公开(公告)日：2010-03-30
申请号：US11350075
申请日：2006-02-09
CPC分类号： H04L63/0853 , H04L63/1441 , H04W12/06 , H04W12/12
摘要： It is made possible to prevent “spoofing” and incur no additional management cost as effectively as possible. An authenticated device includes: at least one authenticated element that generates an output signal with characteristics spontaneously varying, at the time of manufacturing, with respect to a continuous input signal. The characteristics of the authenticated element are used as information unique to an individual.
摘要翻译： 有可能防止“欺骗”，并且不会有效地增加管理成本。 认证设备包括：至少一个认证元件，其在制造时产生具有相对于连续输入信号自发变化的特性的输出信号。 被认证的元素的特征被用作个体唯一的信息。
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公开(公告)号：US08525251B2
公开(公告)日：2013-09-03
申请号：US13221292
申请日：2011-08-30
IPC分类号： H01L29/792
CPC分类号： H01L29/7881 , G11C16/0408 , H01L27/1052 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L27/11807 , H01L29/66825
摘要： A nonvolatile programmable logic switch according to an embodiment includes: a memory cell transistor including: a first source region and a first drain region of a second conductivity type formed at a distance from each other in a first semiconductor region of a first conductivity type; a first insulating film, a charge storage film, a second insulating film, and a control gate stacked in this order and formed on the first semiconductor region between the first source region and the first drain region; a pass transistor including: a second source region and a second drain region of a second conductivity type formed at a distance from each other in a second semiconductor region of the first conductivity type; a third insulating film, a gate electrode stacked in this order and formed on the second semiconductor region between the second source region and the second drain region, the gate electrode being electrically connected to the first drain region; and an electrode for applying a substrate bias to the first and second semiconductor regions.
摘要翻译： 根据实施例的非易失性可编程逻辑开关包括：存储单元晶体管，包括：在第一导电类型的第一半导体区域中彼此间隔开形成的第二导电类型的第一源极区域和第一漏极区域; 第一绝缘膜，电荷存储膜，第二绝缘膜和控制栅极，并且形成在第一源极区域和第一漏极区域之间的第一半导体区域上; 传输晶体管，包括：在第一导电类型的第二半导体区域中彼此成一定距离地形成的第二导电类型的第二源极区域和第二漏极区域; 第三绝缘膜，栅极电极，并且形成在第二源极区域和第二漏极区域之间的第二半导体区域上，栅极电连接到第一漏极区域; 以及用于将衬底偏压施加到第一和第二半导体区域的电极。
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公开(公告)号：US20060212709A1
公开(公告)日：2006-09-21
申请号：US11350075
申请日：2006-02-09
IPC分类号： H04L9/00
CPC分类号： H04L63/0853 , H04L63/1441 , H04W12/06 , H04W12/12
摘要： It is made possible to prevent “spoofing” and incur no additional management cost as effectively as possible. An authenticated device includes: at least one authenticated element that generates an output signal with characteristics spontaneously varying, at the time of manufacturing, with respect to a continuous input signal. The characteristics of the authenticated element are used as information unique to an individual.
摘要翻译： 有可能防止“欺骗”，并且不会有效地增加管理成本。 认证设备包括：至少一个认证元件，其在制造时产生具有相对于连续输入信号自发变化的特性的输出信号。 被认证的元素的特征被用作个体唯一的信息。
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公开(公告)号：US09007823B2
公开(公告)日：2015-04-14
申请号：US13480853
申请日：2012-05-25
IPC分类号： G11C11/34 , H01L21/28 , G11C7/02 , G11C11/403 , H01L29/423 , H01L29/51 , H01L27/108
CPC分类号： H01L21/28291 , G11C7/02 , G11C11/403 , H01L21/28282 , H01L27/108 , H01L27/10873 , H01L29/4234 , H01L29/516
摘要： A semiconductor device according to an embodiment includes: a first transistor including a gate connected to a first interconnection, a first source, and a first drain, one of the first source and the first drain being connected to a second interconnection; and a second transistor including a gate structure, a second source, and a second drain, one of the second source and second drain being connected to a third interconnection and the other of the second source and second drain being connected to a fourth interconnection. The gate structure includes a gate insulation film, a gate electrode, and a threshold-modulating film provided between the gate insulation film and the gate electrode to modulate a threshold voltage, the other of the first source and first drain of the first transistor is connected to the gate electrode.
摘要翻译： 根据实施例的半导体器件包括：第一晶体管，包括连接到第一互连的栅极，第一源极和第一漏极，第一源极和第一漏极中的一个连接到第二互连; 以及第二晶体管，其包括栅极结构，第二源极和第二漏极，所述第二源极和第二漏极中的一个连接到第三互连，并且所述第二源极和第二漏极中的另一个连接到第四互连。 栅极结构包括栅极绝缘膜，栅极电极和设置在栅极绝缘膜和栅电极之间以调节阈值电压的阈值调制膜，第一晶体管的第一源极和第一漏极中的另一个被连接 到栅电极。
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5.发明授权Circuit having programmable match determination function, and LUT circuit, MUX circuit and FPGA device with such function and method of data writing 有权具有可编程匹配确定功能的电路，以及具有数据写入功能和方法的LUT电路，MUX电路和FPGA器件公开(公告)号：US08908408B2
公开(公告)日：2014-12-09
申请号：US13613701
申请日：2012-09-13
申请人： Kosuke Tatsumura , Masato Oda , Atsuhiro Kinoshita , Koichiro Zaitsu , Mari Matsumoto , Shinichi Yasuda
发明人： Kosuke Tatsumura , Masato Oda , Atsuhiro Kinoshita , Koichiro Zaitsu , Mari Matsumoto , Shinichi Yasuda
IPC分类号： G11C15/00
CPC分类号： H03K19/17728 , G11C15/04 , G11C15/046 , H03K19/17712
摘要： A circuit according to embodiments includes: a plurality of bit-string comparators each of which includes a plurality of single-bit comparators each of which includes first and second input terminals, first and second match-determination terminals, and a memory storing data and inverted data in a pair, the first input terminal being connected to a respective search line, the second input terminal being connected to an inverted search line being paired with the respective search line, and a matching line connecting the first and second match-determination terminals of the single-bit comparators; a pre-charge transistor of which source is connected to a supply voltage line; a common matching line connected to a drain of the pre-charge transistor and the matching lines of the bit-string comparators; and an output inverter of which input is connected to the common matching line.
摘要翻译： 根据实施例的电路包括：多个比特串比较器，每个比特串包括多个单比特比较器，每个单比特比较器包括第一和第二输入端，第一和第二匹配确定终端，以及存储数据并反转的存储器 成对的数据，第一输入端子连接到相应的搜索线，第二输入端子连接到与相应搜索线配对的反向搜索线，以及匹配线，连接第一和第二匹配确定端子 单比特比较器; 其源极连接到电源电压线的预充电晶体管; 连接到预充电晶体管的漏极和位串比较器的匹配线的公共匹配线; 以及输入反相器，其输入连接到公共匹配线。
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6.发明授权公开(公告)号：US08546872B2
公开(公告)日：2013-10-01
申请号：US13072366
申请日：2011-03-25
申请人： Kiwamu Sakuma , Atsuhiro Kinoshita
发明人： Kiwamu Sakuma , Atsuhiro Kinoshita
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L27/11524 , H01L27/11551 , H01L29/7881
摘要： According to one embodiment, a memory device includes a semiconductor substrate, first, second, third and fourth fin-type stacked layer structures, each having memory strings stacked in a first direction perpendicular to a surface of the semiconductor substrate, and each extending to a second direction parallel to the surface of the semiconductor substrate, a first part connected to first ends in the second direction of the first and second fin-type stacked layer structures each other, a second part connected to first ends in the second direction of the third and fourth fin-type stacked layer structures each other, a third part connected to second ends in the second direction of the first and third fin-type stacked layer structures each other, and a fourth part connected to second ends in the second direction of the second and fourth fin-type stacked layer structures each other.
摘要翻译： 根据一个实施例，存储器件包括半导体衬底，第一，第二，第三和第四鳍式堆叠层结构，每个具有堆叠在垂直于半导体衬底的表面的第一方向上的存储串，并且每个延伸到 第二方向平行于半导体衬底的表面，第一部分连接到第一和第二鳍式堆叠层的第二方向上的第一端彼此结合，第二部分连接到第三端的第二端 第四鳍状堆叠层结构，第三部分与第一和第三鳍状堆叠层的第二方向的第二端部连接，第四部分与第二鳍片状堆叠层的第二方向的第二端部连接， 第二和第四鳍式堆叠层结构。
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公开(公告)号：US20130252559A1
公开(公告)日：2013-09-26
申请号：US13599413
申请日：2012-08-30
申请人： Jun DEGUCHI , Shouhei Kousai , Yousuke Hagiwara , Masamichi Suzuki , Atsuhiro Kinoshita , Takao Marukame
发明人： Jun DEGUCHI , Shouhei Kousai , Yousuke Hagiwara , Masamichi Suzuki , Atsuhiro Kinoshita , Takao Marukame
IPC分类号： H03M1/66
CPC分类号： H03M1/66 , H03M1/1061 , H03M1/745
摘要： In general, according to one embodiment, a DA converter configured to convert a digital signal comprising n (n>1) bits to an analog current to output the analog current from an output terminal, includes n voltage-current converters. Each of them corresponds to each bit of the digital signal and is configured to generate a current depending on the corresponding bit. A k-th (k is an integer of 0 to n−1) voltage-current converter includes a first transistor whose threshold voltage is adjustable. The first transistor includes a semiconductor substrate, a first diffusion region, a second diffusion region, an insulating film, a charge accumulating film, and a gate.
摘要翻译： 通常，根据一个实施例，配置成将包括n（n> 1）位的数字信号转换为模拟电流以从输出端输出模拟电流的DA转换器包括n个电压 - 电流转换器。 它们中的每一个对应于数字信号的每个位，并且被配置为根据相应的位产生电流。 第k（k是0到n-1的整数）电压 - 电流转换器包括阈值电压可调的第一晶体管。 第一晶体管包括半导体衬底，第一扩散区，第二扩散区，绝缘膜，电荷累积膜和栅极。
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8.发明授权公开(公告)号：US08476690B2
公开(公告)日：2013-07-02
申请号：US13223331
申请日：2011-09-01
IPC分类号： G11C16/04 , H01L29/788
CPC分类号： H01L29/788 , G11C16/0416 , G11C16/0466 , H01L27/11521 , H01L27/11526 , H01L27/11534 , H01L27/11807
摘要： A nonvolatile programmable logic switch according to an embodiment includes: a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type; a memory cell transistor including a first insulating film formed on the first semiconductor region, a charge storage film formed on the first insulating film, a second insulating film formed on the charge storage film, and a control gate formed on the second insulating film; a pass transistor including a third insulating film formed on the second semiconductor region, and a gate electrode formed on the third insulating film and electrically connected to the first drain region; a first electrode applying a substrate bias to the first semiconductor region, the first electrode being formed in the first semiconductor region; and a second electrode applying a substrate bias to the second semiconductor region, the second electrode being formed in the second semiconductor region.
摘要翻译： 根据实施例的非易失性可编程逻辑开关包括：第一导电类型的第一半导体区域和第二导电类型的第二半导体区域; 存储单元晶体管，包括形成在第一半导体区域上的第一绝缘膜，形成在第一绝缘膜上的电荷存储膜，形成在电荷存储膜上的第二绝缘膜，以及形成在第二绝缘膜上的控制栅; 包括形成在第二半导体区域上的第三绝缘膜的通过晶体管和形成在第三绝缘膜上并电连接到第一漏极区的栅电极; 将第一电极施加到所述第一半导体区域的衬底偏压，所述第一电极形成在所述第一半导体区域中; 以及向所述第二半导体区域施加衬底偏压的第二电极，所述第二电极形成在所述第二半导体区域中。
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公开(公告)号：US08450208B2
公开(公告)日：2013-05-28
申请号：US13081629
申请日：2011-04-07
IPC分类号： H01L21/283
CPC分类号： H01L21/28518 , H01L29/1608 , H01L29/41708 , H01L29/456 , H01L29/6606 , H01L29/66068 , H01L29/6609 , H01L29/66272 , H01L29/665 , H01L29/6659 , H01L29/66712 , H01L29/732 , H01L29/7833 , H01L29/861
摘要： In a semiconductor device manufacturing method according to an exemplary embodiment, a sulfur-containing film containing sulfur is deposited on an n-type semiconductor, a first metal film containing a first metal is deposited on the sulfur-containing film, a heat treatment is performed to form a metal semiconductor compound film by reacting the n-type semiconductor and the sulfur-containing film, and to introduce sulfur to an interface between the n-type semiconductor and the metal semiconductor compound film being formed.
摘要翻译： 在根据示例性实施例的半导体器件制造方法中，在n型半导体上沉积含硫的含硫膜，在含硫膜上沉积含有第一金属的第一金属膜，进行热处理 通过使n型半导体和含硫膜反应形成金属半导体化合物膜，并将硫引入到正在形成的n型半导体与金属半导体化合物膜之间的界面上。
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公开(公告)号：US20130042060A1
公开(公告)日：2013-02-14
申请号：US13569605
申请日：2012-08-08
IPC分类号： G06F12/00
CPC分类号： G06F17/30982 , G06F12/0246 , G06F17/30097 , G06F17/3012 , G06F2212/7201
摘要： According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes an interface, a memory block, an address acquisition circuit and a controller. The interface receives a data write/read request or a request based on the key-value store. The memory block has a data area for storing data and a metadata table containing the key-value data. The address acquisition circuit acquires an address in response to input of the key. The controller executes the data write/read request for the memory block, and outputs the address acquired to the memory block and executes the request based on the key-value store. The controller outputs the value corresponding to the key via the interface.
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