公开(公告)号：US07690024B2

公开(公告)日：2010-03-30

申请号：US11350075

申请日：2006-02-09

申请人： Atsuhiro Kinoshita ,  Kazuya Matsuzawa

发明人： Atsuhiro Kinoshita ,  Kazuya Matsuzawa

IPC分类号： G06K19/06 ,  G06F21/00

CPC分类号： H04L63/0853 ,  H04L63/1441 ,  H04W12/06 ,  H04W12/12

摘要： It is made possible to prevent “spoofing” and incur no additional management cost as effectively as possible. An authenticated device includes: at least one authenticated element that generates an output signal with characteristics spontaneously varying, at the time of manufacturing, with respect to a continuous input signal. The characteristics of the authenticated element are used as information unique to an individual.

摘要翻译： 有可能防止“欺骗”，并且不会有效地增加管理成本。 认证设备包括：至少一个认证元件，其在制造时产生具有相对于连续输入信号自发变化的特性的输出信号。 被认证的元素的特征被用作个体唯一的信息。

公开(公告)号：US08525251B2

公开(公告)日：2013-09-03

申请号：US13221292

申请日：2011-08-30

申请人： Daisuke Hagishima ,  Atsuhiro Kinoshita ,  Kazuya Matsuzawa ,  Kazutaka Ikegami ,  Yoshifumi Nishi

发明人： Daisuke Hagishima ,  Atsuhiro Kinoshita ,  Kazuya Matsuzawa ,  Kazutaka Ikegami ,  Yoshifumi Nishi

IPC分类号： H01L29/792

CPC分类号： H01L29/7881 ,  G11C16/0408 ,  H01L27/1052 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11807 ,  H01L29/66825

摘要： A nonvolatile programmable logic switch according to an embodiment includes: a memory cell transistor including: a first source region and a first drain region of a second conductivity type formed at a distance from each other in a first semiconductor region of a first conductivity type; a first insulating film, a charge storage film, a second insulating film, and a control gate stacked in this order and formed on the first semiconductor region between the first source region and the first drain region; a pass transistor including: a second source region and a second drain region of a second conductivity type formed at a distance from each other in a second semiconductor region of the first conductivity type; a third insulating film, a gate electrode stacked in this order and formed on the second semiconductor region between the second source region and the second drain region, the gate electrode being electrically connected to the first drain region; and an electrode for applying a substrate bias to the first and second semiconductor regions.

摘要翻译： 根据实施例的非易失性可编程逻辑开关包括：存储单元晶体管，包括：在第一导电类型的第一半导体区域中彼此间隔开形成的第二导电类型的第一源极区域和第一漏极区域; 第一绝缘膜，电荷存储膜，第二绝缘膜和控制栅极，并且形成在第一源极区域和第一漏极区域之间的第一半导体区域上; 传输晶体管，包括：在第一导电类型的第二半导体区域中彼此成一定距离地形成的第二导电类型的第二源极区域和第二漏极区域; 第三绝缘膜，栅极电极，并且形成在第二源极区域和第二漏极区域之间的第二半导体区域上，栅极电连接到第一漏极区域; 以及用于将衬底偏压施加到第一和第二半导体区域的电极。

公开(公告)号：US20060212709A1

公开(公告)日：2006-09-21

申请号：US11350075

申请日：2006-02-09

申请人： Atsuhiro Kinoshita ,  Kazuya Matsuzawa

发明人： Atsuhiro Kinoshita ,  Kazuya Matsuzawa

IPC分类号： H04L9/00

CPC分类号： H04L63/0853 ,  H04L63/1441 ,  H04W12/06 ,  H04W12/12

摘要： It is made possible to prevent “spoofing” and incur no additional management cost as effectively as possible. An authenticated device includes: at least one authenticated element that generates an output signal with characteristics spontaneously varying, at the time of manufacturing, with respect to a continuous input signal. The characteristics of the authenticated element are used as information unique to an individual.

摘要翻译： 有可能防止“欺骗”，并且不会有效地增加管理成本。 认证设备包括：至少一个认证元件，其在制造时产生具有相对于连续输入信号自发变化的特性的输出信号。 被认证的元素的特征被用作个体唯一的信息。

公开(公告)号：US07834358B2

公开(公告)日：2010-11-16

申请号：US12318739

申请日：2009-01-07

申请人： Kazuya Matsuzawa

发明人： Kazuya Matsuzawa

IPC分类号： H01L27/092 ,  H01L29/41

CPC分类号： H01L29/785 ,  H01L21/28273 ,  H01L21/845 ,  H01L27/0694 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/115 ,  H01L27/1211 ,  H01L29/66787 ,  H01L29/66825 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/788

摘要： Basic logic gates are formed in a small area, and a highly integrated and microscopic structure is provided. In an nMOSFET and a pMOSFET, gate electrodes are formed facing each other and sandwiching a semiconductor region via gate insulting layers. Respective drain regions of the nMOSFET and the pMOSFET are connected to each other. A high potential is applied to a source region of the pMOSFET while an intermediate potential between the high and a low potential is applied to a source region of the nMOSFET. As a result, a NAND gate is provided. The intermediate potential between the high and the low potential is applied to the source region of the pMOSFET. The low potential is applied to the source region of the nMOSFET. As a result, a NOR gate is provided.

摘要翻译： 基本逻辑门形成在小面积上，并提供高度集成和微观结构。 在nMOSFET和pMOSFET中，栅电极形成为彼此面对，并通过栅极绝缘层夹住半导体区域。 nMOSFET和pMOSFET的漏极区彼此连接。 将高电位施加到pMOSFET的源极区域，同时将高电位和低电位之间的中间电位施加到nMOSFET的源极区域。 结果，提供了与非门。 将高电位和低电位之间的中间电位施加到pMOSFET的源极区。 低电位被施加到nMOSFET的源极区域。 结果，提供了NOR门。

公开(公告)号：US20090059669A1

公开(公告)日：2009-03-05

申请号：US12052149

申请日：2008-03-20

申请人： Shuichi Toriyama ,  Kazuya Matsuzawa

发明人： Shuichi Toriyama ,  Kazuya Matsuzawa

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203

摘要： An electrically erasable programmable read-only memory (EEPROM) device of the NAND type having sideface electrodes as auxiliary electrodes on the opposite lateral surfaces of a transistor channel region to thereby improve operation margins is disclosed. The NAND EEPROM, also known as NAND flash memory, has on a semiconductive substrate an array of memory cells including a serial combination of memory cell transistors. Each of memory cell transistors has a pair of source and drain regions, a channel region, a tunnel insulator film, a charge storage layer, a control dielectric film, a control electrode, a sideface dielectric film on the sidefaces of the channel region, and sideface electrodes which are formed on the side surfaces of channel region with the channel region being laterally interposed therebetween. The sideface electrodes are commonized or “shared” by adjacent ones of the serially coupled memory cell transistors.

摘要翻译： 公开了一种NAND型电可擦除可编程只读存储器（EEPROM）器件，其具有在晶体管沟道区域的相对侧表面上的辅助电极的侧面电极，从而提高了操作余量。 NAND EEPROM（也称为NAND闪速存储器）在半导体衬底上具有包括存储单元晶体管的串联组合的存储单元阵列。 每个存储单元晶体管具有一对源极和漏极区，沟道区，隧道绝缘膜，电荷存储层，控制电介质膜，控制电极，沟道区域的侧面上的侧面电介质膜，以及 在通道区域的侧表面上形成有横向插入其间的侧面电极。 侧面电极被串联耦合的存储单元晶体管中的相邻电极共同化或“共享”。

公开(公告)号：US07208933B2

公开(公告)日：2007-04-24

申请号：US11476722

申请日：2006-06-29

申请人： Hiroshi Watanabe ,  Kazuya Matsuzawa ,  Riichiro Shirota

发明人： Hiroshi Watanabe ,  Kazuya Matsuzawa ,  Riichiro Shirota

IPC分类号： G01R19/00

CPC分类号： H01L29/7883 ,  G01R31/2642 ,  G06F9/3802 ,  G06F2221/2137 ,  G06K19/0723 ,  G06K19/073 ,  G06K19/07372 ,  G06Q20/341 ,  G07C9/00111 ,  G07C2009/00976 ,  G07F7/082 ,  G07F7/084 ,  G07F7/1008 ,  G11C16/14 ,  G11C16/349 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/66825

摘要： A time limit function utilization apparatus includes a first function block, a second function block, a signal line which connects the first and second function blocks and allows using a desired function that is generated by accessing the first and second function blocks with each other, and a semiconductor time switch interposed in or connected to the signal line, and disables or enables mutual access between the first and second function blocks upon the lapse of a predetermined time.

公开(公告)号：US20060197111A1

公开(公告)日：2006-09-07

申请号：US11165194

申请日：2005-06-24

申请人： Kazuya Matsuzawa

发明人： Kazuya Matsuzawa

IPC分类号： H01L27/10 ,  H01L21/8238

CPC分类号： H01L29/785 ,  H01L21/28273 ,  H01L21/845 ,  H01L27/0694 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/115 ,  H01L27/1211 ,  H01L29/66787 ,  H01L29/66825 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/788

摘要： Basic logic gates are formed in a small area, and a highly integrated and microscopic structure is provided. In an nMOSFET and a pMOSFET, gate electrodes are formed facing each other and sandwiching a semiconductor region via gate insulting layers. Respective drain regions of the nMOSFET and the pMOSFET are connected to each other. A high potential is applied to a source region of the pMOSFET while an intermediate potential between the high and a low potential is applied to a source region of the nMOSFET. As a result, a NAND gate is provided. The intermediate potential between the high and the low potential is applied to the source region of the pMOSFET. The low potential is applied to the source region of the nMOSFET. As a result, a NOR gate is provided.

公开(公告)号：US20050062071A1

公开(公告)日：2005-03-24

申请号：US10909399

申请日：2004-08-03

申请人： Kazuya Matsuzawa ,  Ken Uchida ,  Takahiro Nakauchi

发明人： Kazuya Matsuzawa ,  Ken Uchida ,  Takahiro Nakauchi

IPC分类号： H01L29/417 ,  H01L21/8244 ,  H01L27/08 ,  H01L27/092 ,  H01L27/11 ,  H01L27/146 ,  H01L27/148

CPC分类号： H01L27/11 ,  H01L27/1104 ,  H01L27/1463 ,  Y10S257/903

摘要： A static random access memory has first and second complementary field-effect transistors. The first complementary field-effect transistor includes a semiconductor substrate, a first field-effect transistor of electron conduction type which has a first drain region constituting a Schottky junction and a gate electrode, and a first field-effect transistor of positive hole conduction type which shares the first drain region and has a shared gate electrode. The second complementary field-effect transistor includes a second field-effect transistor of electron conduction type which has a second drain region and a gate electrode, a second field-effect transistor of positive hole conduction type which shares the second drain region and has a shared gate electrode. The gate electrode shared by the first and second complementary field-effect transistors is connected to the common drain region of the mutually opposing complementary field-effect transistors, and the static random access memory has superior resistance to software errors.

摘要翻译： 静态随机存取存储器具有第一和第二互补场效应晶体管。 第一互补场效应晶体管包括半导体衬底，具有构成肖特基结的第一漏区和栅极的电子传导型的第一场效应晶体管和正空穴传导型的第一场效应晶体管， 共享第一漏极区域并具有共用栅电极。 第二互补场效应晶体管包括具有第二漏极区和栅极的电子传导型的第二场效应晶体管，共享第二漏极区并具有共享的空穴导体型的第二场效应晶体管 栅电极。 由第一和第二互补场效应晶体管共享的栅电极连接到相互相对的互补场效应晶体管的公共漏区，并且静态随机存取存储器具有优异的软件误差抵抗能力。

公开(公告)号：US20100250223A1

公开(公告)日：2010-09-30

申请号：US12652434

申请日：2010-01-05

申请人： Daisuke Hagishima ,  Kazuya Matsuzawa ,  Yuichiro Mitani ,  Shigeto Fukatsu ,  Kouichirou Inoue

发明人： Daisuke Hagishima ,  Kazuya Matsuzawa ,  Yuichiro Mitani ,  Shigeto Fukatsu ,  Kouichirou Inoue

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A semiconductor circuit deterioration simulation method for a circuit including MOSFETs includes inserting a dynamic voltage source associated with a fluctuation in voltage/current characteristics into each gate terminal of a plurality of MOSFETs in series, calculating dynamic deterioration amounts of the plurality of MOSFETs by performing circuit simulation and calculating a dynamic deterioration amount, and repeating the above processing to perform the circuit deterioration simulation over the long term.

摘要翻译： 包括MOSFET的电路的半导体电路劣化模拟方法包括将与电压/电流特性波动相关联的动态电压源串联插入到多个MOSFET的每个栅极端子中，通过执行电路来计算多个MOSFET的动态劣化量 模拟并计算动态劣化量，并且重复上述处理以长期执行电路恶化模拟。

公开(公告)号：US20090015074A1

公开(公告)日：2009-01-15

申请号：US12049715

申请日：2008-03-17

申请人： Hiroshi WATANABE ,  Kazuya Matsuzawa

发明人： Hiroshi WATANABE ,  Kazuya Matsuzawa

IPC分类号： H01H7/00

CPC分类号： G06F21/85 ,  G06F21/71 ,  G06F2221/2137 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/18 ,  H01L27/105 ,  H01L27/11526 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  Y10T307/951 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

摘要： An electronic device includes a substrate, a first chip mounted on the substrate and having a first terminal, a second terminal, an input pad and a semiconductor time switch connected to the first terminal and the second terminal and configured to disconnect the first terminal and the second terminal upon lapse of a prescribed lifetime, the input pad being configured to set the prescribed lifetime, a second chip mounted on the substrate and incorporating an operational device having a third terminal connected to the first terminal and a fourth terminal serving as an input terminal for an external device, a first memory device mounted on the substrate, having a fifth terminal connected to the second terminal and storing information required for operating the operational device, and an encapsulater covering at least the input pad of the first chip.

摘要翻译： 电子设备包括：基板，安装在基板上的第一芯片，具有连接到第一端子和第二端子的第一端子，第二端子，输入焊盘和半导体时间开关，并被配置为断开第一端子和 第二端子经过规定的寿命时，输入焊盘被配置为设定规定的寿命，安装在基板上的第二芯片并且包括具有连接到第一端子的第三端子的操作装置和用作输入端子的第四端子 对于外部设备，安装在基板上的第一存储器件，具有连接到第二端子的第五端子并且存储操作操作器件所需的信息，以及至少覆盖第一芯片的输入焊盘的封装器。