公开(公告)号：US07095672B2

公开(公告)日：2006-08-22

申请号：US10852288

申请日：2004-05-25

申请人： Atsunori Miki

发明人： Atsunori Miki

IPC分类号： G11C8/00

CPC分类号： G11C16/349

摘要： A semiconductor memory device includes a plurality of memory blocks formed of a flash memory. The semiconductor memory device further includes a rewriting monitor circuit for memorizing the number of times of data rewriting in each of the memory blocks, and a switching circuit for switching a memory block selection address. When the number of times of rewriting in a first memory block which is a rewriting request object exceeds a predetermined value, data in a second memory block is transferred to the first memory block. Data to be written is written to the second memory block. Therefore, it is possible to increase the number of times of rewriting in the flash memory.

摘要翻译： 半导体存储器件包括由闪速存储器形成的多个存储器块。 半导体存储器件还包括用于存储每个存储块中的数据重写次数的重写监视电路和用于切换存储块选择地址的切换电路。 当在作为重写请求对象的第一存储器块中重写次数超过预定值时，第二存储块中的数据被传送到第一存储块。 要写入的数据被写入第二存储块。 因此，可以增加闪速存储器中的重写次数。

公开(公告)号：US20100013449A1

公开(公告)日：2010-01-21

申请号：US12458623

申请日：2009-07-17

申请人： Atsunori Miki

发明人： Atsunori Miki

IPC分类号： G05F1/00

CPC分类号： G05F1/56

摘要： Disclosed is a regulator including: a differential amplifier having a differential input stage receiving a reference voltage and an output terminal voltage, a push-pull type output portion of a current mirror configuration, a drive transistor having a control terminal connected to an output portion of the differential amplifier, first and second transistors cascode-connected between a control terminal of the drive transistor and a power supply, and third and fourth transistors cascode-connected between the control terminal of the drive transistor and ground. Control terminals of the first and the third transistors are respectively connected to control terminals of the push-pull transistors, control terminals of the second and fourth transistors are respectively connected to a first and a second control signal. A voltage of the control terminal of the drive transistor is controlled, based on the first and the second control signals, by output of the differential amplifier and the first transistor, or by output of the differential amplifier and the third transistor.

摘要翻译： 公开了一种调节器，包括：差分放大器，其具有接收参考电压和输出端电压的差分输入级，电流镜配置的推挽型输出部分，驱动晶体管，其具有连接到输出部分的输出部分的控制端子 串联连接在驱动晶体管的控制端和电源之间的差分放大器，第一和第二晶体管，以及串联连接在驱动晶体管的控制端和地之间的第三和第四晶体管。 第一和第三晶体管的控制端分别连接到推挽晶体管的控制端，第二和第四晶体管的控制端分别连接到第一和第二控制信号。 基于第一和第二控制信号，通过差分放大器和第一晶体管的输出，或通过差分放大器和第三晶体管的输出来控制驱动晶体管的控制端子的电压。

公开(公告)号：US07042788B2

公开(公告)日：2006-05-09

申请号：US11087663

申请日：2005-03-24

申请人： Atsunori Miki

发明人： Atsunori Miki

IPC分类号： G11C7/00

CPC分类号： G11C5/145

摘要： A semiconductor storage device for driving a word line by a voltage higher than an external supply voltage that includes a boost circuit for outputting a boosted voltage of a first electric potential by boosting the external power supply potential, an auxiliary capacitor for storing the output potential of the boost circuit at the time of a standby state, a switch for supplying to a word line driving power supply line a second electric potential obtained by voltage dividing the first electric potential at the time of the standby and being turned off at the time of an operation, and an amplifier circuit for receiving the first electric potential as a driving power supply potential and driving the word line driving power supply line by the second electric potential at the time of the operation.

摘要翻译： 一种用于通过高于外部电源电压的电压来驱动字线的半导体存储装置，该外部电源电压包括用于通过升高外部电源电位来输出第一电位的升高电压的升压电路，用于存储输出电位的辅助电容器 在待机状态下的升压电路，用于向字线驱动电源线提供在待机时分压第一电位而获得的第二电位的开关，并且在第二电位 以及放大电路，用于接收第一电位作为驱动电源电位，并且在操作时驱动字线驱动电源线的第二电位。

公开(公告)号：US06788600B2

公开(公告)日：2004-09-07

申请号：US10139716

申请日：2002-05-06

申请人： Hiroshi Sugawara ,  Toshikatsu Jinbo ,  Atsunori Miki ,  Takayuki Kurokawa ,  Kenichi Ushikoshi

发明人： Hiroshi Sugawara ,  Toshikatsu Jinbo ,  Atsunori Miki ,  Takayuki Kurokawa ,  Kenichi Ushikoshi

IPC分类号： G11C702

CPC分类号： G11C7/18 ,  G11C5/025

摘要： A non-volatile flash memory (100) that may have an improved layout freedom is disclosed. Non-volatile flash memory (100) may include banks (B0 and B1). Each bank (B0 and B1) may include memory cell arrays (MCA00 to MCA03) including a plurality of memory cells (MC) connected to sub bit lines (LB). A plurality of sub bit lines (LB) may be selectively connected to a main bit line (MB) by a group switch (Y1S0 and Y1S1). A group of main bit lines (MB) may be disposed over a memory cell array. A group of main bit lines (MB) may be selectively connected to a sense amplifier block (SAB) by a group switch group (Y2S0 and Y2S1) and a bank switch group (Y3S0 and Y3S1). In this way, a sense amplifier block (SAB) may be shared by a plurality of groups of main bit lines (MB). In this way, layout freedom may be improved.

摘要翻译： 公开了可以具有改进的布局自由度的非易失性闪存（100）。 非易失性闪存（100）可以包括存储体（B0和B1）。 每个存储体（B0和B1）可以包括包括连接到子位线（LB）的多个存储单元（MC）的存储单元阵列（MCA00至MCA03）。 多个子位线（LB）可以通过组开关（Y1S0和Y1S1）选择性地连接到主位线（MB）。 一组主位线（MB）可以设置在存储单元阵列上。 一组主位线（MB）可以通过组开关组（Y2S0和Y2S1）和组开关组（Y3S0和Y3S1）选择性地连接到读出放大器模块（SAB）。 以这种方式，读出放大器块（SAB）可以被多个主位线组（MB）共享。 以这种方式，可以提高布局自由度。

公开(公告)号：US07948809B2

公开(公告)日：2011-05-24

申请号：US12458623

申请日：2009-07-17

申请人： Atsunori Miki

发明人： Atsunori Miki

IPC分类号： G11C5/14

CPC分类号： G05F1/56

摘要： Disclosed is a regulator including: a differential amplifier having a differential input stage receiving a reference voltage and an output terminal voltage, a push-pull type output portion of a current mirror configuration, a drive transistor having a control terminal connected to an output portion of the differential amplifier, first and second transistors cascode-connected between a control terminal of the drive transistor and a power supply, and third and fourth transistors cascode-connected between the control terminal of the drive transistor and ground. Control terminals of the first and the third transistors are respectively connected to control terminals of the push-pull transistors, control terminals of the second and fourth transistors are respectively connected to a first and a second control signal. A voltage of the control terminal of the drive transistor is controlled, based on the first and the second control signals, by output of the differential amplifier and the first transistor, or by output of the differential amplifier and the third transistor.

摘要翻译： 公开了一种调节器，包括：差分放大器，具有接收参考电压和输出端电压的差分输入级，电流镜配置的推挽型输出部分，驱动晶体管，具有连接到输出部分的输出部分的控制端子 串联连接在驱动晶体管的控制端和电源之间的差分放大器，第一和第二晶体管，以及串联连接在驱动晶体管的控制端和地之间的第三和第四晶体管。 第一和第三晶体管的控制端分别连接到推挽晶体管的控制端，第二和第四晶体管的控制端分别连接到第一和第二控制信号。 基于第一和第二控制信号，通过差分放大器和第一晶体管的输出，或通过差分放大器和第三晶体管的输出来控制驱动晶体管的控制端子的电压。

公开(公告)号：US20050002238A1

公开(公告)日：2005-01-06

申请号：US10852288

申请日：2004-05-25

申请人： Atsunori Miki

发明人： Atsunori Miki

IPC分类号： G11C16/02 ,  G11C16/34 ,  G11C11/34

CPC分类号： G11C16/349

摘要： A semiconductor memory device includes a plurality of memory blocks formed of a flash memory. The semiconductor memory device further includes a rewriting monitor circuit for memorizing the number of times of data rewriting in each of the memory blocks, and a switching circuit for switching a memory block selection address. When the number of times of rewriting in a first memory block which is a rewriting request object exceeds a predetermined value, data in a second memory block is transferred to the first memory block. Data to be written is written to the second memory block. Therefore, it is possible to increase the number of times of rewriting in the flash memory.

摘要翻译： 半导体存储器件包括由闪速存储器形成的多个存储器块。 半导体存储器件还包括用于存储每个存储块中的数据重写次数的重写监视电路和用于切换存储块选择地址的切换电路。 当在作为重写请求对象的第一存储器块中重写次数超过预定值时，第二存储块中的数据被传送到第一存储块。 要写入的数据被写入第二存储块。 因此，可以增加闪速存储器中的重写次数。

公开(公告)号：US06256250B1

公开(公告)日：2001-07-03

申请号：US09507672

申请日：2000-02-22

申请人： Atsunori Miki

发明人： Atsunori Miki

IPC分类号： G11C700

CPC分类号： G11C5/14 ,  G11C5/145

摘要： Disclosed is a power supply circuit that, at a first node, generates a read voltage and a write voltage for a memory cell. According to the present invention, a power supply circuit comprises: a boosting circuit, for boosting to a first voltage the voltage at the first node when a writing operation is initiated; a capacitor, one end of which is connected to the first node and the other end of which is connected to a second node; a driver circuit, for changing from a second to a third voltage the voltage at the first node when a reading operation is initiated; and a connection circuit, for electrically connecting the first node to the second node when the writing operation is initiated.

摘要翻译： 公开了一种电源电路，其在第一节点处产生用于存储单元的读取电压和写入电压。 根据本发明，电源电路包括：升压电路，用于在写入操作开始时将第一电压的电压升压到第一电压;电容器，其一端连接到第一节点和 其另一端连接到第二节点;驱动器电路，用于当开始读取操作时，从第二电压变为第三电压;第一节点处的电压; 和连接电路，用于在开始写入操作时将第一节点电连接到第二节点。

公开(公告)号：US6121821A

公开(公告)日：2000-09-19

申请号：US280972

申请日：1999-03-30

申请人： Atsunori Miki

发明人： Atsunori Miki

IPC分类号： G11C16/06 ,  G11C5/14 ,  H02M3/07 ,  H01L25/00

CPC分类号： G11C5/145

摘要： A booster circuit is disclosed, the booster circuit having a plurality of booster cells tandem-connected, each of the boosters having a transfer transistor and a capacitor, an input terminal, a drain, and a gate of the transfer transistor being connected, a source of the transfer transistor being an output terminal, a first terminal of the capacitor being connected to the source of the transfer transistor, a clock signal being supplied to a second terminal of the capacitor, wherein the transfer transistor is composed of a triple-well having a first well and a second well, the first well being formed on a semiconductor substrate, the second well being formed on the first well, and wherein the semiconductor substrate is connected to a reference voltage, a diffusion layer in the first well, a first diffusion layer in the second well, a second diffusion layer in the second well, the first terminal of the capacitor, and the gate of the transfer transistor being connected, the conduction type of the first well being the same as the conduction type of the diffusion layer in the first well, the conduction type of the second well being the same as the conduction type of the first diffusion layer in the second well, the conduction type of the second well being different from the conduction type of the second diffusion layer in the second well.

摘要翻译： 公开了一种升压电路，升压电路具有串联连接的多个升压电池，每个升压器具有传输晶体管和电容器，连接的传输晶体管的输入端子，漏极和栅极，源极 所述转移晶体管是输出端子，所述电容器的第一端子连接到所述传输晶体管的源极，所述时钟信号被提供给所述电容器的第二端子，其中所述传输晶体管由三阱组成，所述三阱具有 第一阱和第二阱，第一阱形成在半导体衬底上，第二阱形成在第一阱上，并且其中半导体衬底连接到参考电压，第一阱中的扩散层，第一阱 第二阱中的扩散层，第二阱中的第二扩散层，电容器的第一端子和传输晶体管的栅极被连接，导通型 第一阱的导电类型与第一阱中的扩散层的导电类型相同，第二阱的导电类型与第二阱中的第一扩散层的导电类型相同，导电类型 第二阱与第二阱中的第二扩散层的导电类型不同。

公开(公告)号：US5998831A

公开(公告)日：1999-12-07

申请号：US936803

申请日：1997-09-24

申请人： Noriaki Kodama ,  Kiyokazu Ishige ,  Atsunori Miki ,  Toshikatsu Jinbo ,  Kazuhisa Ninomiya

发明人： Noriaki Kodama ,  Kiyokazu Ishige ,  Atsunori Miki ,  Toshikatsu Jinbo ,  Kazuhisa Ninomiya

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L29/788

CPC分类号： G11C16/30

摘要： A plurality of memory cells are arranged in lattice arrangement to form a memory cell array. Each of the memory cells is provided with a source. Data in the memory cell can be electrically written and erased. Sources of all the memory cells are connected in common. Also, a source voltage control circuit having two or more kinds of load characteristics is connected to the sources connected in common. According to a load characteristics selected from a plurality of load characteristics, source voltage of the memory cell is controlled.

摘要翻译： 多个存储单元以格子排列布置以形成存储单元阵列。 每个存储单元都有一个源。 存储单元中的数据可以被电写入和擦除。 所有存储器单元的源头共同连接。 此外，具有两种或多种负载特性的源极电压控制电路连接到共同连接的源极。 根据从多个负载特性中选择的负载特性，控制存储单元的源极电压。

公开(公告)号：US5895958A

公开(公告)日：1999-04-20

申请号：US668908

申请日：1996-06-24

申请人： Atsunori Miki

发明人： Atsunori Miki

IPC分类号： H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/90

CPC分类号： H01L27/0251

摘要： In an input protection circuit, a bipolar protection device is constituted of a semiconductor substrate of a first conductivity type, a first diffused layer of a second conductivity type formed in the substrate and connected to an input signal pad, a second diffused layer of the second conductivity type formed in the substrate to extend in parallel to the first diffused layer but separately from the first diffused layer by a first space, and a third diffused layer of a high impurity concentration and of the first conductivity type formed in the first space in the substrate to extend in parallel to the first and second diffused layers, in junction with the second diffused layer but separately from the first diffused layer. When a backward biasing voltage is applied, the thickness of a depletion layer formed is made large, so that generation of hot carriers is minimized. Thus, increase of a leakage current caused because hot carriers generated by application of an overvoltage were injected into a field oxide film, can be prevented.

摘要翻译： 在输入保护电路中，双极性保护器件由第一导电类型的半导体衬底，形成在衬底中的第二导电类型的第一扩散层构成，并连接到输入信号焊盘，第二扩散层的第二扩散层 导电型形成在基板上，与第一扩散层平行延伸，但与第一扩散层分开，第一空间，以及形成在第一空间中的第一导电类型的第三扩散层， 衬底，以平行于第一和第二扩散层延伸，与第二扩散层结合，但与第一扩散层分开。 当施加反向偏置电压时，形成的耗尽层的厚度变大，使得热载流子的产生最小化。 因此，可以防止由于施加过电压而产生的热载流子引起的漏电流的增加被注入到场氧化膜中。