公开(公告)号：US06788600B2

公开(公告)日：2004-09-07

申请号：US10139716

申请日：2002-05-06

申请人： Hiroshi Sugawara ,  Toshikatsu Jinbo ,  Atsunori Miki ,  Takayuki Kurokawa ,  Kenichi Ushikoshi

发明人： Hiroshi Sugawara ,  Toshikatsu Jinbo ,  Atsunori Miki ,  Takayuki Kurokawa ,  Kenichi Ushikoshi

IPC分类号： G11C702

CPC分类号： G11C7/18 ,  G11C5/025

摘要： A non-volatile flash memory (100) that may have an improved layout freedom is disclosed. Non-volatile flash memory (100) may include banks (B0 and B1). Each bank (B0 and B1) may include memory cell arrays (MCA00 to MCA03) including a plurality of memory cells (MC) connected to sub bit lines (LB). A plurality of sub bit lines (LB) may be selectively connected to a main bit line (MB) by a group switch (Y1S0 and Y1S1). A group of main bit lines (MB) may be disposed over a memory cell array. A group of main bit lines (MB) may be selectively connected to a sense amplifier block (SAB) by a group switch group (Y2S0 and Y2S1) and a bank switch group (Y3S0 and Y3S1). In this way, a sense amplifier block (SAB) may be shared by a plurality of groups of main bit lines (MB). In this way, layout freedom may be improved.

摘要翻译： 公开了可以具有改进的布局自由度的非易失性闪存（100）。 非易失性闪存（100）可以包括存储体（B0和B1）。 每个存储体（B0和B1）可以包括包括连接到子位线（LB）的多个存储单元（MC）的存储单元阵列（MCA00至MCA03）。 多个子位线（LB）可以通过组开关（Y1S0和Y1S1）选择性地连接到主位线（MB）。 一组主位线（MB）可以设置在存储单元阵列上。 一组主位线（MB）可以通过组开关组（Y2S0和Y2S1）和组开关组（Y3S0和Y3S1）选择性地连接到读出放大器模块（SAB）。 以这种方式，读出放大器块（SAB）可以被多个主位线组（MB）共享。 以这种方式，可以提高布局自由度。

公开(公告)号：US5998831A

公开(公告)日：1999-12-07

申请号：US936803

申请日：1997-09-24

申请人： Noriaki Kodama ,  Kiyokazu Ishige ,  Atsunori Miki ,  Toshikatsu Jinbo ,  Kazuhisa Ninomiya

发明人： Noriaki Kodama ,  Kiyokazu Ishige ,  Atsunori Miki ,  Toshikatsu Jinbo ,  Kazuhisa Ninomiya

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L29/788

CPC分类号： G11C16/30

摘要： A plurality of memory cells are arranged in lattice arrangement to form a memory cell array. Each of the memory cells is provided with a source. Data in the memory cell can be electrically written and erased. Sources of all the memory cells are connected in common. Also, a source voltage control circuit having two or more kinds of load characteristics is connected to the sources connected in common. According to a load characteristics selected from a plurality of load characteristics, source voltage of the memory cell is controlled.

摘要翻译： 多个存储单元以格子排列布置以形成存储单元阵列。 每个存储单元都有一个源。 存储单元中的数据可以被电写入和擦除。 所有存储器单元的源头共同连接。 此外，具有两种或多种负载特性的源极电压控制电路连接到共同连接的源极。 根据从多个负载特性中选择的负载特性，控制存储单元的源极电压。

公开(公告)号：US08570098B2

公开(公告)日：2013-10-29

申请号：US13569247

申请日：2012-08-08

申请人： Toshikatsu Jinbo

发明人： Toshikatsu Jinbo

IPC分类号： G05F1/10

CPC分类号： G05F1/565

摘要： A voltage reducing circuit includes an internal power supply section configured to reduce an external power supply voltage supplied from an external power supply to an internal power supply voltage which is lower than the external power supply voltage based on a reference voltage. A first current control section is configured to control a current flowing through the internal power supply section when the internal power supply voltage is lower than a setting voltage. A second current control section is configured to control the current flowing through the internal power supply section when the internal power supply voltage exceeds the setting voltage.

摘要翻译： 电压降低电路包括：内部电源部，被配置为基于参考电压将从外部电源提供的外部电源电压降低到低于外部电源电压的内部电源电压。 第一电流控制部被配置为当内部电源电压低于设定电压时，控制流过内部电源部的电流。 第二电流控制部被配置为当内部电源电压超过设定电压时，控制流过内部电源部的电流。

公开(公告)号：US20100085088A1

公开(公告)日：2010-04-08

申请号：US12585499

申请日：2009-09-16

申请人： Toshikatsu Jinbo

发明人： Toshikatsu Jinbo

IPC分类号： H03L7/00

CPC分类号： G06F1/24

摘要： Provided is a semiconductor device including a step-down circuit group including multiple step-down circuits that step down an external power supply voltage to a predetermined voltage; multiple functional circuits that require a reset operation upon power-on; and a power-on reset circuit that outputs a reset command to the multiple functional circuits, when an internal power supply voltage supplied from the step-down circuit group exceeds a voltage level necessary for an initialization operation. The multiple step-down circuits of the step-down circuit group are classified into a startup operating step-down circuit group that performs a step-down operation from power-on to supply the internal power supply voltage, and a startup non-operating step-down circuit group that stops operation upon power-on to interrupt supply of the internal power supply voltage. The startup non-operating step-down circuit group includes the multiple step-down circuits sequentially selected from one having a shortest wiring distance from the power-on reset circuit.

摘要翻译： 提供一种包括降压电路组的半导体器件，包括将外部电源电压降低到预定电压的多个降压电路; 上电时需要复位操作的多个功能电路; 以及当从降压电路组提供的内部电源电压超过初始化操作所需的电压电平时，向多个功能电路输出复位指令的上电复位电路。 降压电路组的多个降压电路分为启动操作降压电路组，其从上电执行降压操作以提供内部电源电压，以及启动非操作步骤 断电电路组在上电时停止工作，中断内部电源电压供电。 启动非操作降压电路组包括从具有与上电复位电路相距最短布线距离的多个降压电路中顺次选择的多个降压电路。

公开(公告)号：US06788562B2

公开(公告)日：2004-09-07

申请号：US10328435

申请日：2002-12-23

申请人： Teiichiro Nishizaka ,  Toshikatsu Jinbo ,  Takaki Kohno

发明人： Teiichiro Nishizaka ,  Toshikatsu Jinbo ,  Takaki Kohno

IPC分类号： G11C700

CPC分类号： G11C17/126 ,  G11C7/18 ,  G11C16/0475 ,  G11C16/0491 ,  H01L27/115

摘要： Disclosed is a device and a method for enabling a programmable semiconductor memory device to provide a block selection transistor of a high voltage withstand type, to prevent the voltage from being decreased at the time of programming, to prevent the readout current from being decreased and to provide a constant sum resistance of the electrically conductive regions without dependency upon the memory cell locations.

摘要翻译： 公开了一种用于使可编程半导体存储器件能够提供高耐压型的块选择晶体管的装置和方法，以防止在编程时电压降低，以防止读出电流减小，并且 提供导电区域的恒定的和电阻，而不依赖于存储器单元位置。

公开(公告)号：US06608781B1

公开(公告)日：2003-08-19

申请号：US09650158

申请日：2000-08-28

申请人： Toshikatsu Jinbo ,  Kazuo Watanabe

发明人： Toshikatsu Jinbo ,  Kazuo Watanabe

IPC分类号： G11C700

CPC分类号： G11C16/30 ,  G11C16/0416 ,  G11C16/10

摘要： According to the present invention, a voltage of 10.5 V, a voltage of 6.5 V and a voltage of 0.5 V are respectively applied to the control gate, the drain and the source of a memory cell that is a programming target. And a voltage of 0 V (a ground voltage) is applied to the control gate of a memory cell that is not a programming target and that does not belong to the row in which of the programming target memory cell is located. As a result, it is ensured that the memory cell that is not the programming target is non-conductive, and that the drain-substrate electrical field of the memory cell that is the programming target is reduced.

摘要翻译： 根据本发明，作为编程对象的存储单元的控制栅极，漏极和源极分别施加10.5V的电压，6.5V的电压和0.5V的电压。 并且将不是编程对象的不属于编程对象存储单元的行的存储单元的控制栅极施加0V的电压（接地电压）。 结果，确保不是编程对象的存储单元是非导通的，并且减小作为编程对象的存储单元的漏极 - 基板电场。

公开(公告)号：US5313086A

公开(公告)日：1994-05-17

申请号：US934275

申请日：1992-08-25

申请人： Toshikatsu Jinbo

发明人： Toshikatsu Jinbo

IPC分类号： H01L27/088 ,  G11C16/14 ,  H01L21/8234 ,  H01L21/8236 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/092 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/68

CPC分类号： H01L29/7885 ,  G11C16/14

摘要： A semiconductor device includes a P-type semiconductor substrate, an N-type well region formed on the surface of the substrate, a P-type well region formed in the N-type well region and a MOSFET as a flash memory element formed in the P-type well region. Upon erasure of the information in the flash memory, a high voltage is temporarily charged to the P-type and N-type well regions, in such a manner that a first high voltage pulse of a predetermined width is charged to the N-type well region, a second high voltage pulse having a pulse width narrower than the pulse width of the first pulse is charged to the P-type well region in a period between the initiation end and the termination end of the first pulse.

摘要翻译： 半导体器件包括P型半导体衬底，形成在衬底表面上的N型阱区，形成在N型阱区中的P型阱区和形成在该N型阱区中的闪存元件的MOSFET P型井区。 在擦除闪速存储器中的信息时，将高电压暂时充电到P型和N型阱区，使得将预定宽度的第一高电压脉冲充电到N型阱 区域中，在第一脉冲的起始端和终止端之间的时段内，将具有比第一脉冲宽度窄的脉冲宽度的第二高电压脉冲充电到P型阱区。

公开(公告)号：US4947378A

公开(公告)日：1990-08-07

申请号：US194615

申请日：1988-05-16

申请人： Toshikatsu Jinbo ,  Hiroyuki Kobatake

发明人： Toshikatsu Jinbo ,  Hiroyuki Kobatake

IPC分类号： G11C16/06 ,  G11C17/00 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/789

摘要： A redundant address memory circuit is used in a memory element exchange circuit associated to a memory matrix composed of FAMOS memory cells and provided with a redundant memory array composed of FAMOS memory cells. The redundant address memory circuit comprises a FAMOS memory cell for storing a defective address, and an output circuit connected to the defective address storing FAMOS memory cell for generating an output signal corresponding to the content of the defective address storing FAMOS memory cell. In addition, there is provided a circuit connected to the defective address storing FAMOS memory cell and to the output circuit for receiving the content of the defective address storing FAMOS memory cell through the output circuit so as to write the content of the defective address storing FAMOS memory cell into the defective address storing FAMOS memory cell when a new data is written to the memory matrix.

摘要翻译： 冗余地址存储器电路用于与由FAMOS存储器单元组成的存储器矩阵相关联并且具有由FAMOS存储器单元组成的冗余存储器阵列的存储元件交换电路。 冗余地址存储器电路包括用于存储缺陷地址的FAMOS存储单元，以及连接到存储FAMOS存储单元的缺陷地址的输出电路，用于产生与存储FAMOS存储单元的缺陷地址的内容相对应的输出信号。 此外，提供了连接到不良地址存储FAMOS存储单元的电路和输出电路，用于通过输出电路接收存储FAMOS存储单元的缺陷地址的内容，以便写入存储FAMOS的缺陷地址的内容 当将新数据写入存储器矩阵时，存储器单元进入存储FAMOS存储单元的缺陷地址。

公开(公告)号：US07868641B2

公开(公告)日：2011-01-11

申请号：US12200940

申请日：2008-08-29

申请人： Toshikatsu Jinbo

发明人： Toshikatsu Jinbo

IPC分类号： G01R31/02 ,  G01R31/28

CPC分类号： G01R31/31718 ,  G11C29/06 ,  G11C29/48 ,  G11C29/50

摘要： A semiconductor device with technology for externally deciding if the stress test was performed or not. A semiconductor device includes a stress test circuit and a stress test decision circuit. The stress test circuit outputs control signals for executing the stress test to the stress test decision circuit and the object for testing. The stress test decision circuit then outputs the decision results if the stress test was performed, based on the control signals.

摘要翻译： 一种具有外部决定是否进行应力测试的技术的半导体器件。 半导体器件包括应力测试电路和应力测试判定电路。 应力测试电路将用于执行应力测试的控制信号输出到应力测试判定电路和测试对象。 然后，根据控制信号，应力测试判定电路如果进行了应力测试，则输出判定结果。

公开(公告)号：US07660085B2

公开(公告)日：2010-02-09

申请号：US11358226

申请日：2006-02-22

申请人： Hiroshi Furuta ,  Kenji Hibino ,  Hidetaka Natsume ,  Toshikatsu Jinbo ,  Kiyokazu Hashimoto

发明人： Hiroshi Furuta ,  Kenji Hibino ,  Hidetaka Natsume ,  Toshikatsu Jinbo ,  Kiyokazu Hashimoto

IPC分类号： H02H3/22

CPC分类号： G11C5/14

摘要： A conventional layout of power supply protective element cannot sufficiently protect an internal circuit against a surge current that flows into a narrow branch line that branches off from a thick main wiring line. A semiconductor device according to an embodiment of the present invention includes a power supply protective element connected around a terminal; a main wiring line connected with a VCC pad or a GND pad; a branch line that branches off from the main wiring line and applies a power supply potential or a ground potential to a functional block of the semiconductor device; a branching portion at which the branch line branches off from the main wiring line; and an internal power supply protective element connected with the branch line.

摘要翻译： 电源保护元件的常规布局不能充分地保护内部电路免受流入从厚主布线分支的窄支线的浪涌电流的影响。 根据本发明的实施例的半导体器件包括围绕端子连接的电源保护元件; 与VCC焊盘或GND焊盘连接的主要配线; 从主布线分支的分支线，向半导体器件的功能块施加电源电位或地电位; 分支部分，其分支线从主布线分支; 以及与分支线连接的内部电源保护元件。