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    Non-volatile semiconductor memory
    1.
    发明授权
    Non-volatile semiconductor memory 有权
    非易失性半导体存储器

    公开(公告)号：US06788600B2

    公开(公告)日：2004-09-07

    申请号：US10139716

    申请日：2002-05-06

    申请人： Hiroshi Sugawara ,  Toshikatsu Jinbo ,  Atsunori Miki ,  Takayuki Kurokawa ,  Kenichi Ushikoshi

    发明人： Hiroshi Sugawara ,  Toshikatsu Jinbo ,  Atsunori Miki ,  Takayuki Kurokawa ,  Kenichi Ushikoshi

    IPC分类号： G11C702

    CPC分类号： G11C7/18 ,  G11C5/025

    摘要： A non-volatile flash memory (100) that may have an improved layout freedom is disclosed. Non-volatile flash memory (100) may include banks (B0 and B1). Each bank (B0 and B1) may include memory cell arrays (MCA00 to MCA03) including a plurality of memory cells (MC) connected to sub bit lines (LB). A plurality of sub bit lines (LB) may be selectively connected to a main bit line (MB) by a group switch (Y1S0 and Y1S1). A group of main bit lines (MB) may be disposed over a memory cell array. A group of main bit lines (MB) may be selectively connected to a sense amplifier block (SAB) by a group switch group (Y2S0 and Y2S1) and a bank switch group (Y3S0 and Y3S1). In this way, a sense amplifier block (SAB) may be shared by a plurality of groups of main bit lines (MB). In this way, layout freedom may be improved.

    摘要翻译： 公开了可以具有改进的布局自由度的非易失性闪存（100）。 非易失性闪存（100）可以包括存储体（B0和B1）。 每个存储体（B0和B1）可以包括包括连接到子位线（LB）的多个存储单元（MC）的存储单元阵列（MCA00至MCA03）。 多个子位线（LB）可以通过组开关（Y1S0和Y1S1）选择性地连接到主位线（MB）。 一组主位线（MB）可以设置在存储单元阵列上。 一组主位线（MB）可以通过组开关组（Y2S0和Y2S1）和组开关组（Y3S0和Y3S1）选择性地连接到读出放大器模块（SAB）。 以这种方式，读出放大器块（SAB）可以被多个主位线组（MB）共享。 以这种方式，可以提高布局自由度。

    Semiconductor memory device and data storage method including address conversion circuit to convert coordinate information of data into one-dimensional information to amplifier
    2.
    发明授权
    Semiconductor memory device and data storage method including address conversion circuit to convert coordinate information of data into one-dimensional information to amplifier 失效
    半导体存储器件和数据存储方法包括将数据的坐标信息转换为放大器的一维信息的地址转换电路

    公开(公告)号：US07907473B2

    公开(公告)日：2011-03-15

    申请号：US12216673

    申请日：2008-07-09

    申请人： Tatsuya Ishizaki ,  Hironori Nakamura ,  Takayuki Kurokawa ,  Kenichi Ushikoshi

    发明人： Tatsuya Ishizaki ,  Hironori Nakamura ,  Takayuki Kurokawa ,  Kenichi Ushikoshi

    IPC分类号： G11C8/00

    CPC分类号： G11C8/10 ,  G11C7/1006 ,  G11C8/12

    摘要： A semiconductor memory device for storing data defining a multidimensional space based on coordinate information of the data, includes: a cell array having memory cells arranged in a lattice pattern, for storing the data; a word line selector selecting and driving any one of a plurality of word lines which activate memory cells arranged in a row direction; write amplifiers/sense amplifiers writing/reading data to/from the memory cells arranged in a column direction; an amplifier selector inputting/outputting the data to/from the selected one of the write amplifiers/sense amplifiers; and an address conversion circuit generating a row address to be supplied to the word line selector based on the coordinate information of the data, and to generate a column address to be supplied to the amplifier selector by converting the coordinate information of the data into one-dimensional information.

    摘要翻译： 一种用于存储基于数据的坐标信息定义多维空间的数据的半导体存储器件，包括：具有以格子图案排列的存储单元的单元阵列，用于存储数据; 选择并驱动激活沿行方向布置的存储单元的多个字线中的任一个的字线选择器; 写放大器/读出放大器向/从布置在列方向上的存储单元写入/读取数据; 一个放大器选择器，输入/输出来自所选择的一个写入放大器/读出放大器的数据; 以及地址转换电路，其基于数据的坐标信息产生要提供给字线选择器的行地址，并且通过将数据的坐标信息转换为一维地生成要提供给放大器选择器的列地址， 尺寸信息。

    Semiconductor memory device and data storage method
    3.
    发明申请
    Semiconductor memory device and data storage method 失效
    半导体存储器件和数据存储方法

    公开(公告)号：US20090027993A1

    公开(公告)日：2009-01-29

    申请号：US12216673

    申请日：2008-07-09

    申请人： Tatsuya Ishizaki ,  Hironori Nakamura ,  Takayuki Kurokawa ,  Kenichi Ushikoshi

    发明人： Tatsuya Ishizaki ,  Hironori Nakamura ,  Takayuki Kurokawa ,  Kenichi Ushikoshi

    IPC分类号： G11C8/00

    CPC分类号： G11C8/10 ,  G11C7/1006 ,  G11C8/12

    摘要： According to an aspect of the present invention, there is provided a semiconductor memory device for storing data defining a multidimensional space based on coordinate information of the data, including: a cell array having memory cells arranged in a lattice pattern, for storing the data; a word line selector selecting and driving any one of a plurality of word lines which activate memory cells arranged in a row direction; write amplifiers/sense amplifiers writing/reading data to/from the memory cells arranged in a column direction; an amplifier selector inputting/outputting the data to/from the selected one of the write amplifiers/sense amplifiers; and an address conversion circuit generating a row address to be supplied to the word line selector based on the coordinate information of the data, and to generate a column address to be supplied to the amplifier selector by converting the coordinate information of the data into one-dimensional information.

    摘要翻译： 根据本发明的一个方面，提供了一种用于存储基于数据的坐标信息定义多维空间的数据的半导体存储器件，包括：具有以格子图案排列的存储单元的单元阵列，用于存储数据; 选择并驱动激活沿行方向布置的存储单元的多个字线中的任一个的字线选择器; 写放大器/读出放大器向/从布置在列方向上的存储单元写入/读取数据; 一个放大器选择器，输入/输出来自所选择的一个写入放大器/读出放大器的数据; 以及地址转换电路，其基于数据的坐标信息产生要提供给字线选择器的行地址，并且通过将数据的坐标信息转换为一维地生成要提供给放大器选择器的列地址， 尺寸信息。

    Semiconductor level shifter circuit
    4.
    发明授权
    Semiconductor level shifter circuit 有权
    半导体电平转换电路

    公开(公告)号：US06646918B2

    公开(公告)日：2003-11-11

    申请号：US10054085

    申请日：2002-01-22

    申请人： Takayuki Kurokawa ,  Hiroshi Sugawara

    发明人： Takayuki Kurokawa ,  Hiroshi Sugawara

    IPC分类号： G11C1134

    CPC分类号： G11C16/12

    摘要： A level shifter (1) that may provide a relatively high-speed operation in a level shifting mode and a non-level shifting mode has been disclosed. Level shifter (1) may include a transistor (P101) providing a controllable current path between a voltage terminal (3) and an output signal (TOUT) based on the logic level of an input signal (IN). Series connected transistors (P104 and P105) may provide a controllable current path between voltage terminal (3) and output signal (TOUT) based on the logic level of an input signal (IN). Transistor (P105) may be enabled in a Vcc mode and may be disabled in a Vpp mode. In this way, an equivalent transistor width (WT) may be adjusted in accordance with a mode of operation and a transition time of output signal (TOUT) may be improved.

    摘要翻译： 已经公开了可以在电平移位模式和非电平移位模式中提供相对高速操作的电平移位器（1）。 电平移位器（1）可以包括基于输入信号（IN）的逻辑电平提供电压端（3）和输出信号（TOUT）之间的可控电流路径的晶体管（P101）。 串联连接的晶体管（P104和P105）可以基于输入信号（IN）的逻辑电平提供电压端（3）和输出信号（TOUT）之间的可控电流路径。 晶体管（P105）可以在Vcc模式下使能，并且可以在Vpp模式下禁用。 以这种方式，可以根据工作模式来调整等效晶体管宽度（WT），并且可以提高输出信号（TOUT）的转换时间。

    Semiconductor integrated circuit device which has first chip and second chip accessed via the first chip and test method thereof
    5.
    发明申请
    Semiconductor integrated circuit device which has first chip and second chip accessed via the first chip and test method thereof 失效
    具有通过第一芯片访问的第一芯片和第二芯片的半导体集成电路器件及其测试方法

    公开(公告)号：US20090167337A1

    公开(公告)日：2009-07-02

    申请号：US12314689

    申请日：2008-12-15

    申请人： Kazunori Yamane ,  Takayuki Kurokawa ,  Yuji Tada ,  Hironori Nakamura ,  Manabu Kitabatake

    发明人： Kazunori Yamane ,  Takayuki Kurokawa ,  Yuji Tada ,  Hironori Nakamura ,  Manabu Kitabatake

    IPC分类号： G01R31/303

    CPC分类号： G11C29/48 ,  G11C29/1201 ,  G11C2029/0401 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device includes a first chip including an internal circuit, and a second chip capable of being accessed only via the first chip, and a test processor circuit electrically connected internally via the first chip, for accessing the second chip from an external terminal and testing the second chip, and a test circuit where an input/output buffer is installed for signals for accessing the second chip within the test processor circuit, and a bypass line installed for transferring signals from the first chip to the second chip and avoiding the input/output buffer within the test processor circuit, and a switch which switches between signal transfer path via the input/output buffer, and a signal transfer path via the bypass line.

    摘要翻译： 半导体集成电路器件包括：第一芯片，其包括内部电路;以及第二芯片，其仅能够经由第一芯片访问;以及测试处理器电路，其经由第一芯片内部电连接，用于从外部端子访问第二芯片 并且测试第二芯片，以及测试电路，其中安装了用于访问测试处理器电路内的第二芯片的信号的输入/输出缓冲器，以及安装用于将信号从第一芯片传送到第二芯片并且避免 测试处理器电路内的输入/输出缓冲器，以及通过输入/输出缓冲器在信号传送路径和通过旁路线路的信号传送路径之间切换的开关。

    Optical scanning head-mounted display and retinal scanning head-mounted display
    6.
    发明授权
    Optical scanning head-mounted display and retinal scanning head-mounted display 有权

    公开(公告)号：US10257478B2

    公开(公告)日：2019-04-09

    申请号：US15704478

    申请日：2017-09-14

    申请人： Takayuki Kurokawa

    发明人： Takayuki Kurokawa

    IPC分类号： H04N3/08 ,  H04N9/31 ,  H04N5/232 ,  G02B27/01 ,  H04N7/01 ,  G02B26/10

    摘要： An optical scanning head-mounted display includes a head mount unit including a light source that emits a light beam, an optical scanner that scans the light beam to irradiate the light beam onto a projection plane, an image capturing device that outputs image data of a captured image as the image data in a first format, and an interface that converts the image data in the first format obtained from the image capturing device into the image data in a second format and outputs the image data in the second format; a transmission cable that transmits the image data in the second format; and a controller that receives the image data in the second format through the transmission cable and controls the emission of the light beam from the light source based on the image data in the second format.

    Semiconductor integrated circuit device which has first chip and second chip accessed via the first chip and test method thereof
    7.
    发明授权
    Semiconductor integrated circuit device which has first chip and second chip accessed via the first chip and test method thereof 失效
    具有通过第一芯片访问的第一芯片和第二芯片的半导体集成电路器件及其测试方法

    公开(公告)号：US08289041B2

    公开(公告)日：2012-10-16

    申请号：US12314689

    申请日：2008-12-15

    申请人： Kazunori Yamane ,  Takayuki Kurokawa ,  Yuji Tada ,  Hironori Nakamura ,  Manabu Kitabatake

    发明人： Kazunori Yamane ,  Takayuki Kurokawa ,  Yuji Tada ,  Hironori Nakamura ,  Manabu Kitabatake

    IPC分类号： G01R31/3187

    CPC分类号： G11C29/48 ,  G11C29/1201 ,  G11C2029/0401 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device includes a first chip including an internal circuit, and a second chip capable of being accessed only via the first chip, and a test processor circuit electrically connected internally via the first chip, for accessing the second chip from an external terminal and testing the second chip, and a test circuit where an input/output buffer is installed for signals for accessing the second chip within the test processor circuit, and a bypass line installed for transferring signals from the first chip to the second chip and avoiding the input/output buffer within the test processor circuit, and a switch which switches between signal transfer path via the input/output buffer, and a signal transfer path via the bypass line.

    摘要翻译： 半导体集成电路器件包括：第一芯片，其包括内部电路;以及第二芯片，其仅能够经由第一芯片访问;以及测试处理器电路，其经由第一芯片内部电连接，用于从外部端子访问第二芯片 并且测试第二芯片，以及测试电路，其中安装了用于访问测试处理器电路内的第二芯片的信号的输入/输出缓冲器，以及安装用于将信号从第一芯片传送到第二芯片并且避免 测试处理器电路内的输入/输出缓冲器，以及通过输入/输出缓冲器在信号传送路径和通过旁路线路的信号传送路径之间切换的开关。

    Semiconductor device
    9.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US08405219B2

    公开(公告)日：2013-03-26

    申请号：US13490871

    申请日：2012-06-07

    申请人： Yuji Tada ,  Tsuyoshi Hirakawa ,  Hironori Nakamura ,  Takayuki Kurokawa

    发明人： Yuji Tada ,  Tsuyoshi Hirakawa ,  Hironori Nakamura ,  Takayuki Kurokawa

    IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

    摘要： A semiconductor device, includes a substrate, a multi-layer wiring layer formed on the substrate, and including a signal line and ground lines extending above the signal line, one of the ground lines extending toward a direction in a predetermined layer and another one of the ground lines extending from the one of the ground lines toward another direction in the predetermined layer, a first pad on the multi-layer wiring layer, a redistribution layer formed on the multi-layer wiring layer, including a second pad, a redistribution line coupling the first and second pads, and an insulation film covering the redistribution line, the redistribution line extending above the ground lines along the one of the ground lines and not extending along the another one of the ground lines. The insulation film includes a hole exposing the second pad above an end portion of the one of the ground lines.