利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

162 条记录 (耗时 0.036 秒)

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20120112191A1

    公开(公告)日：2012-05-10

    申请号：US13270455

    申请日：2011-10-11

    申请人： Kiyoshi KATO ,  Yutaka SHIONOIRI ,  Shuhei NAGATSUKA ,  Yuto YAKUBO ,  Jun KOYAMA

    发明人： Kiyoshi KATO ,  Yutaka SHIONOIRI ,  Shuhei NAGATSUKA ,  Yuto YAKUBO ,  Jun KOYAMA

    IPC分类号： H01L29/16

    CPC分类号： H01L27/1156 ,  G11C11/403 ,  G11C16/0433 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1225 ,  H01L28/40

    摘要： A data retention period in a semiconductor device or a semiconductor memory device is lengthened. The semiconductor device or the semiconductor memory includes a memory circuit including a first transistor including a first semiconductor layer and a first gate and a second transistor including a second semiconductor layer, a second gate, and a third gate The first semiconductor layer is formed at the same time as a layer including the second gate.

    摘要翻译： 半导体器件或半导体存储器件中的数据保持期延长。 半导体器件或半导体存储器包括存储电路，该存储器电路包括第一晶体管，其包括第一半导体层和第一栅极，第二晶体管包括第二半导体层，第二栅极和第三栅极。第一半导体层形成在 与包括第二门的层相同。

    THIN FILM CIRCUIT
    6.
    发明申请
    THIN FILM CIRCUIT 失效
    薄膜电路

    公开(公告)号：US20060267018A1

    公开(公告)日：2006-11-30

    申请号：US11462886

    申请日：2006-08-07

    申请人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Hisashi OHTANI

    发明人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Hisashi OHTANI

    IPC分类号： H01L29/76

    CPC分类号： H01L29/04 ,  H01L21/02532 ,  H01L21/02672 ,  H01L27/12 ,  H01L27/1277 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78675

    摘要： A practical operational amplifier circuit is formed using thing film transisters. An operational amplifier circuit is formed by thin film transistors formed on a quartz substrate wherein cumulative distribution of mobilities of the n-channel type thin film transistors becomes 90% or more at 260 cm2/Vs and wherein cumulative distribution of mobilities of the p-channel type thin film transistors becomes 90% or more at 150 cm2/Vs. The thin film transistors have active layers formed using a crystalline silicon film fabricated using a metal element that selected to promote crystallization of silicon. The crystalline silicon film is a collection of a multiplicity of elongate crystal structures extending in a certain direction, and the above-described characteristics can be achieved by matching the extending direction and the moving direction of carriers.

    摘要翻译： 使用物体转换器形成实际的运算放大器电路。 运算放大器电路由形成在石英衬底上的薄膜晶体管形成，其中n沟道型薄膜晶体管的迁移率的累积分布在260cm 2 / Vs处变为90％以上，其中累积 p沟道型薄膜晶体管的迁移率的分布在150cm 2 / Vs下变为90％以上。 薄膜晶体管具有使用使用选择促进硅的结晶的金属元素制造的晶体硅膜形成的有源层。 结晶硅膜是沿一定方向延伸的多个细长晶体结构的集合，并且可以通过匹配载流子的延伸方向和移动方向来实现上述特性。

    Non-Volatile Memory and Semiconductor Device
    8.
    发明申请
    Non-Volatile Memory and Semiconductor Device 有权
    非易失性存储器和半导体器件

    公开(公告)号：US20090180326A1

    公开(公告)日：2009-07-16

    申请号：US12407539

    申请日：2009-03-19

    申请人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

    发明人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

    IPC分类号： G11C16/06

    CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32

    摘要： There is provided a non-volatile memory which enables high accuracy threshold control in a writing operation. In the present invention, a drain voltage and a drain current of a memory transistor are controlled to carry out a writing operation of a hot electron injection system, which is wherein a charge injection speed does not depend on a threshold voltage. FIGS. 1A and 1B are views of a circuit structure for controlling the writing. In FIGS. 1A and 1B, an output of an operational amplifier 103 is connected to a control gate of a memory transistor 101, a constant current source 102 is connected to a drain electrode, and a source electrode is grounded. The constant current source 102 and a voltage Vpgm are respectively connected to two input terminals of the operational amplifier 103.

    摘要翻译： 提供了一种在写入操作中实现高精度阈值控制的非易失性存储器。 在本发明中，控制存储晶体管的漏极电压和漏极电流，进行热电子注入系统的写入动作，其中电荷注入速度不依赖于阈值电压。 图 图1A和1B是用于控制写入的电路结构的视图。 在图 如图1A和1B所示，运算放大器103的输出连接到存储晶体管101的控制栅极，恒流源102连接到漏电极，源电极接地。 恒流源102和电压Vpgm分别连接到运算放大器103的两个输入端。

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20110101334A1

    公开(公告)日：2011-05-05

    申请号：US12912190

    申请日：2010-10-26

    申请人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

    发明人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

    IPC分类号： H01L27/108

    CPC分类号： H01L27/088 ,  G11C11/404 ,  G11C11/405 ,  G11C16/02 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1225

    摘要： It is an object to provide a semiconductor having a novel structure. In the semiconductor device, a plurality of memory elements are connected in series and each of the plurality of memory elements includes first to third transistors thus forming a memory circuit. A source or a drain of a first transistor which includes an oxide semiconductor layer is in electrical contact with a gate of one of a second and a third transistor. The extremely low off current of a first transistor containing the oxide semiconductor layer allows storing, for long periods of time, electrical charges in the gate electrode of one of the second and the third transistor, whereby a substantially permanent memory effect can be obtained. The second and the third transistors which do not contain an oxide semiconductor layer allow high-speed operations when using the memory circuit.

    摘要翻译： 本发明的目的是提供具有新颖结构的半导体。 在半导体器件中，多个存储器元件串联连接，并且多个存储元件中的每一个包括第一至第三晶体管，从而形成存储器电路。 包括氧化物半导体层的第一晶体管的源极或漏极与第二和第三晶体管之一的栅极电接触。 含有氧化物半导体层的第一晶体管的极低的截止电流允许长时间地在第二和第三晶体管之一的栅电极中存储电荷，由此可以获得基本上永久的记忆效应。 不含氧化物半导体层的第二和第三晶体管在使用存储电路时允许高速操作。

    DATA PROCESSING DEVICE, IC CARD AND COMMUNICATION SYSTEM
    10.
    发明申请
    DATA PROCESSING DEVICE, IC CARD AND COMMUNICATION SYSTEM 有权
    数据处理设备，IC卡和通信系统

    公开(公告)号：US20100253478A1

    公开(公告)日：2010-10-07

    申请号：US12754416

    申请日：2010-04-05

    申请人： Jun KOYAMA ,  Kiyoshi KATO ,  Shunpei YAMAZAKI

    发明人： Jun KOYAMA ,  Kiyoshi KATO ,  Shunpei YAMAZAKI

    IPC分类号： H04Q5/22

    CPC分类号： H04W52/028 ,  Y02D70/122 ,  Y02D70/166

    摘要： An object is to provide a data processing device which achieves multiple functions or easy additional providing of a function while suppressing adverse influence on a communication distance or to improve resistance to electrostatic discharge in the data processing device. The data processing device includes an antenna which transmits and receives a first signal to/from a first terminal device through wireless communication, an integrated circuit which executes a process in accordance with the first signal, and a terminal portion which transmits and receives a second signal to/from a second terminal device and has an exposed conductive portion on its surface. A protection circuit is provided between at least one terminal of terminals of the terminal portion and a power supply terminal of a high potential and between the one terminal and a power supply terminal of a low potential.

    摘要翻译： 本发明的目的是提供一种能够实现多种功能的数据处理装置，或容易地附加提供功能，同时抑制对通信距离的不利影响或提高数据处理装置中的静电放电的抵抗力。 数据处理装置包括通过无线通信向第一终端装置发送第一信号的接收天线，执行与第一信号对应的处理的集成电路以及发送接收第二信号的终端部 到/从第二终端设备，并且在其表面上具有暴露的导电部分。 在端子部分的端子的至少一个端子和高电位的电源端子之间以及在一个端子和低电位的电源端子之间提供保护电路。