摘要:
A method for manufacturing a bladder for use in manufacturing tires having a surface-modified rubber layer on an outer surface side of a base rubber layer, including the steps of: forming an uncross-linked body of the surface-modified rubber layer by molding a rubber composition including a modified butyl rubber composition and an organic peroxide and applying a siloxane compound having a (meth)acryloyl group to a surface of this rubber molded body; forming the base rubber layer from an unvulcanized body or vulcanized body formed from a rubber composition different than the modified butyl rubber composition; laminating the uncross-linked body of the surface-modified rubber layer on the outer surface side of the base rubber layer; and heat treating.
摘要:
A method for manufacturing a bladder for use in manufacturing tires having a surface-modified rubber layer on an outer surface side of a base rubber layer, including the steps of: forming an uncross-linked body of the surface-modified rubber layer by molding a rubber composition including a modified butyl rubber composition and an organic peroxide and applying a siloxane compound having a (meth)acryloyl group to a surface of this rubber molded body; forming the base rubber layer from an unvulcanized body or vulcanized body formed from a rubber composition different than the modified butyl rubber composition; laminating the uncross-linked body of the surface-modified rubber layer on the outer surface side of the base rubber layer; and heat treating.
摘要:
The present invention is a command or data transfer between two integrated circuit devices (hereafter LSIs) wherein an LSI issuing a command or data (issuing side LSI) outputs a strobe signal, which indicates that a valid command or data was transmitted, to the LSI which receives the command or data (receiving side LSI), and the receiving side LSI outputs a signal, which notifies that the command processing completed (command ready signal), to the issuing side LSI. The issuing side LSI comprises a counter where a value to indicate the number of commands which the receiving side LSI can simultaneously process or simultaneously receive is loaded at initialization, wherein the counter is decremented when a command or data is issued, the counter is incremented when the ready signal is received, and issuing a command or data is inhibited when the counter becomes “0”. Therefore the issuing side LSI can issue a command or data to the receiving side LSI without confirming a busy signal from the receiving side LSI.
摘要:
In a processor, an operating unit executes an instruction within an instruction set, and a second operating unit executes other custom instructions. The second operating unit consists of a plurality of AND circuits, OR circuits, adders, selectors, and multiplexers. The information about which circuit should be combined with which circuit when the instruction is input is held in advance as structure information in a configuration memory. One piece of structure information corresponds to one custom instruction. The second operating unit in an optimum circuit structure determined based on this structure information executes the instruction. With this arrangement, it is possible to increase the processing speed than when the operating unit executes the processing.
摘要:
A flexible magnetic disk drive is disclosed which has a stepper motor coupled to a data transducer via a steel belt motion translating mechanism for moving the transducer from track to track on the rotating disk in response to stepping pulses and a stepping direction signal from an external host system. In order to save power, the stepper motor is held deenergized while the disk drive motor is out of rotation, with the consequent possibility that the transducer may be displaced from the required track position on the disk while the stepper motor is held deenergized. Therefore, in order to always memorize the latest of the successive destination tracks commanded by the host system, a forward/backward counter is provided which counts the external stepping pulses in either direction depending upon the binary state of the external stepping direction signal. After the disk drive motor is set into rotation, stepping pulses and an stepping direction signal are generated internally for causing the stepper motor to automatically reposition the transducer on the memorized latest destination track.
摘要:
A vane pump comprising a housing having front and rear surfaces and formed with a cam ring housing portion which is open to the front surface, the housing being further formed at its inner peripheral wall with recess portions and an axial bore extending from the rear surface, said axial bore being open to a center of the ring housing portion; a drive shaft freely rotatably supported in the axial bore of the housing; a rotor inserted on the drive shaft and engaged with the drive shaft, the rotor having a plurality of slits and a plurality of vanes each projectable from and retractable in the corresponding slit; a cam ring having at its inner peripheral wall a cam surface which is arranged to enclose the rotor therein and form pump chambers in cooperation with the vanes, the cam ring being formed at its outer peripheral wall with recess portions of substantially semicircular configuration in cross section; a front end plate by which the cam ring is closed at its one end; a rear end plate formed with a bearing portion through which one end portion of the drive shaft is freely rotatably supported, the rear end plate also formed with at least a pair of openings, each of the openings being spaced at a predetermined distance from a center axis of the bearing portion of the rear end plate; and knock pins fixedly inserted in the openings of the rear end plate, disposed to engage the cam ring in the semicircular recess portions of the cam ring, and disposed with clearance in bores defined by the recess portions of the housing so that the cam ring is held and positioned only with respect to the rear end plate.
摘要:
A circuit for data transfer includes a first buffer operating at a first clock frequency, a plurality of second buffers operating at a second clock frequency, and a selector circuit which receives data at the first clock frequency, and supplies the data to a selected one of the first buffer and the second buffers.
摘要:
The present invention is a command or data transfer between two integrated circuit devices (hereafter LSIS) wherein an LSI issuing a command or data (issuing side LSI) outputs a strobe signal, which indicates that a valid command or data was transmitted, to the LSI which receives the command or data (receiving side LSI), and the receiving side LSI outputs a signal, which notifies that the command processing completed (command ready signal), to the issuing side LSI. The issuing side LSI comprises a counter where a value to indicate the number of commands which the receiving side LSI can simultaneously process or simultaneously receive is loaded at initialization, wherein the counter is decremented when a command or data is issued, the counter is incremented when the ready signal is received, and issuing a command or data is inhibited when the counter becomes “0”. Therefore the issuing side LSI can issue a command or data to the receiving side LSI without confirming a busy signal from the receiving side LSI.
摘要:
In a cache memory control method and computer of the present invention, a cache memory is connected to a main memory and divided into a plurality of cache blocks, and a lock/unlock signal is supplied to the cache memory to either set a replace-inhibition state of at least one of the cache blocks in which replacing at least one of the cache blocks to the main memory is inhibited, or reset the replace-inhibition state of at least one of the cache clocks such that replacing at least one of the cache block to the main memory is allowed. Either reading or writing of the main memory is performed by using the remaining cache blocks of the cache memory, other than the at least one of the cache blocks, such that, when the replace-inhibition state is set by the lock/unlock signal, replacing the at least one of the cache blocks to the main memory is inhibited during the reading or writing of the main memory.