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1.发明申请Apparatus and Method for Determining the Number of Execution Units to Keep Active in a Processor 审中-公开用于确定在处理器中保持活动的执行单元数量的装置和方法公开(公告)号：US20150241954A1
公开(公告)日：2015-08-27
申请号：US14697553
申请日：2015-04-27
申请人： Avinash N. Ananthakrishnan , Julien Sebot , Jay D. Schwartz , Stephen H. Gunther , Eric C. Samson
发明人： Avinash N. Ananthakrishnan , Julien Sebot , Jay D. Schwartz , Stephen H. Gunther , Eric C. Samson
IPC分类号： G06F1/32
CPC分类号： G06F1/3293 , G06F1/3206 , G06F1/324 , G06F1/3287 , Y02D10/122 , Y02D10/126 , Y02D10/171
摘要： A processor is described that includes a plurality of execution units in a processor core. The processor also may include power management circuitry to determine a configuration with a lowest power cost from a plurality of configurations that each have a different number of enabled execution units for a same active performance state. A method may include determining with power management circuitry of a processor a configuration with a lowest power cost from a plurality of configurations that each have a different number of enabled execution units in a processor core of the processor for a same active performance state.
摘要翻译： 描述了在处理器核心中包括多个执行单元的处理器。 处理器还可以包括功率管理电路，以从多个配置中确定具有最低功率成本的配置，每个配置对于相同的主动性能状态具有不同数量的启用的执行单元。 一种方法可以包括：通过处理器的功率管理电路确定来自多个配置的具有最低功率成本的配置，每个配置在处理器的处理器核心中具有不同数量的启用的执行单元，用于相同的主动性能状态。
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2.发明授权Apparatus and method for determining the number of execution cores to keep active in a processor 有权用于确定在处理器中保持活动的执行核心数量的装置和方法公开(公告)号：US09037889B2
公开(公告)日：2015-05-19
申请号：US13631679
申请日：2012-09-28
申请人： Avinash N. Ananthakrishnan , Julien Fefe Sebot , Jay D. Schwartz , Stephen H. Gunther , Eric C. Samson
发明人： Avinash N. Ananthakrishnan , Julien Fefe Sebot , Jay D. Schwartz , Stephen H. Gunther , Eric C. Samson
IPC分类号： G06F1/32
CPC分类号： G06F1/3293 , G06F1/3206 , G06F1/324 , G06F1/3287 , Y02D10/122 , Y02D10/126 , Y02D10/171
摘要： A processor is described that includes a plurality of execution cores. The processor also includes power management circuitry to dynamically determine a number of the execution cores that, when active, will cause the processor to operate in a substantially linear power consumption vs. frequency region of operation such that performance gain as a function of power consumption increase with the number of cores is higher as compared to any other number of active execution cores within an established power envelope.
摘要翻译： 描述了包括多个执行核心的处理器。 处理器还包括电源管理电路，用于动态地确定许多执行核心，当激活时，这些核心将使处理器在基本上线性的功率消耗与频率操作区域中工作，使得作为功率消耗的功能的性能增益 与所建立的功率范围内的任何其他数量的主动执行核心相比，核心数量更高。
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3.发明申请Apparatus and Method For Determining the Number of Execution Cores To Keep Active In A Processor 有权用于确定在处理器中保持活动的执行核心数量的装置和方法公开(公告)号：US20140095904A1
公开(公告)日：2014-04-03
申请号：US13631679
申请日：2012-09-28
申请人： Avinash N. Ananthakrishnan , Julien Fefe Sebot , Jay D. Schwartz , Stephen H. Gunther , Eric C. Samson
发明人： Avinash N. Ananthakrishnan , Julien Fefe Sebot , Jay D. Schwartz , Stephen H. Gunther , Eric C. Samson
IPC分类号： G06F1/32
CPC分类号： G06F1/3293 , G06F1/3206 , G06F1/324 , G06F1/3287 , Y02D10/122 , Y02D10/126 , Y02D10/171
摘要： A processor is described that includes a plurality of execution cores. The processor also includes power management circuitry to dynamically determine a number of the execution cores that, when active, will cause the processor to operate in a substantially linear power consumption vs. frequency region of operation such that performance gain as a function of power consumption increase with the number of cores is higher as compared to any other number of active execution cores within an established power envelope.
摘要翻译： 描述了包括多个执行核心的处理器。 处理器还包括电源管理电路，用于动态地确定许多执行核心，当激活时，这些核心将使处理器在基本上线性的功率消耗与频率操作区域中工作，使得作为功率消耗的功能的性能增益 与所建立的功率范围内的任何其他数量的主动执行核心相比，核心数量更高。
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公开(公告)号：US20150095620A1
公开(公告)日：2015-04-02
申请号：US14039151
申请日：2013-09-27
IPC分类号： G06F9/30
CPC分类号： G06F9/30083 , G06F1/3206 , G06F1/324 , G06F1/3275 , G06F1/3287 , G06F1/3296 , G06F9/4893 , G06F11/3466 , G06F12/084 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： In an embodiment, a processor includes a first logic to calculate a scalability value for a processor domain based at least in part on an active state residency, a stall duration, and a memory bandwidth of the domain, and to determine an operating frequency update for the domain based at least in part on a current operating frequency of the domain and the scalability value. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器包括第一逻辑，用于至少部分地基于所述域的活动状态驻留，停止持续时间和存储器带宽来计算处理器域的可扩展性值，并且确定用于 该域至少部分地基于域的当前操作频率和可扩展性值。 描述和要求保护其他实施例。
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公开(公告)号：US20140068293A1
公开(公告)日：2014-03-06
申请号：US13783978
申请日：2013-03-04
申请人： Xiuting C. Man , Michael N. Derr , Jay D. Schwartz , Stephen H. Gunther , Jeremy J. Shrall , Shaun M. Conrad , Avinash N. Ananthakrishnan
发明人： Xiuting C. Man , Michael N. Derr , Jay D. Schwartz , Stephen H. Gunther , Jeremy J. Shrall , Shaun M. Conrad , Avinash N. Ananthakrishnan
IPC分类号： G06F1/32
CPC分类号： G06F1/32 , G06F1/206 , G06F1/3206 , G06F1/324 , Y02D10/126
摘要： In an embodiment, a processor includes a first domain with at least one core to execute instructions and a second domain coupled to the first domain and including at least one non-core circuit. These domains can operate at independent frequencies, and a power control unit coupled to the domains may include a thermal logic to cause a reduction in a frequency of the first domain responsive to occurrence of a thermal event in the second domain. Other embodiments are described and claimed.
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6.发明授权Controlling operating frequency of a core domain via a non-core domain of a multi-domain processor 有权通过多域处理器的非核心域控制核心域的操作频率公开(公告)号：US09026815B2
公开(公告)日：2015-05-05
申请号：US13282947
申请日：2011-10-27
申请人： Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Jeremy J. Shrall , Eric C. Samson , Eliezer Wiessmann , Ryan Wells
发明人： Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Jeremy J. Shrall , Eric C. Samson , Eliezer Wiessmann , Ryan Wells
CPC分类号： G06F1/324 , G06F1/26 , G06F1/30 , G06F1/3203 , G06F1/3234 , G06F1/3243 , G06F13/14 , Y02D10/126
摘要： In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于确定多域处理器的非核心域不以非核域所请求的频率操作的方法，将来自非核心域的请求发送到功率 控制器降低多域处理器核心域的频率，并响应请求，降低核心域频率。 描述和要求保护其他实施例。
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7.发明申请公开(公告)号：US20130111236A1
公开(公告)日：2013-05-02
申请号：US13282947
申请日：2011-10-27
申请人： Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Jeremy J. Shrall , Eric C. Samson , Eliezer Wiessman , Ryan Wells
发明人： Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Jeremy J. Shrall , Eric C. Samson , Eliezer Wiessman , Ryan Wells
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/26 , G06F1/30 , G06F1/3203 , G06F1/3234 , G06F1/3243 , G06F13/14 , Y02D10/126
摘要： In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.
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8.发明申请Method, Apparatus, and System for Energy Efficiency and Energy Conservation Through Dynamic Management of Memory and Input/Output Subsystems 审中-公开通过动态管理存储器和输入/输出子系统的能量效率和节能的方法，装置和系统公开(公告)号：US20120095607A1
公开(公告)日：2012-04-19
申请号：US13335638
申请日：2011-12-22
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3253 , Y02D10/151
摘要： According to one embodiment of the invention, an integrated circuit device comprises an interconnect, at least one compute engine and a control unit. Coupled to the at least one compute engine via the interconnect, the control unit to analyze heuristic information from the at least one compute engine and to increase or decrease a bandwidth of the interconnect based on the heuristic information.
摘要翻译： 根据本发明的一个实施例，集成电路设备包括互连，至少一个计算引擎和控制单元。 所述控制单元经由所述互连耦合到所述至少一个计算引擎，以分析来自所述至少一个计算引擎的启发式信息，并且基于所述启发式信息来增加或减少所述互连的带宽。
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9.发明申请Controlling Operating Frequency Of A Core Domain Via A Non-Core Domain Of A Multi-Domain Processor 审中-公开通过多域处理器的非核心域控制核心域的工作频率公开(公告)号：US20130179709A1
公开(公告)日：2013-07-11
申请号：US13782578
申请日：2013-03-01
申请人： Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Jeremy J. Shrall , Eric C. Samson , Eliezer Wiessmann , Ryan Wells
发明人： Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Jeremy J. Shrall , Eric C. Samson , Eliezer Wiessmann , Ryan Wells
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/26 , G06F1/30 , G06F1/3203 , G06F1/3234 , G06F1/3243 , G06F13/14 , Y02D10/126
摘要： In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于确定多域处理器的非核心域不以非核域所请求的频率操作的方法，将来自非核心域的请求发送到功率 控制器降低多域处理器核心域的频率，并响应请求，降低核心域频率。 描述和要求保护其他实施例。
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公开(公告)号：US20210064426A1
公开(公告)日：2021-03-04
申请号：US16554940
申请日：2019-08-29
IPC分类号： G06F9/48 , G06F1/3206 , G06F9/50 , G06F1/08 , G06F1/10
摘要： In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first maximum operating point for the first core and a second maximum operating point for the at least one second core based at least in part on the scaled power budget; determine a first efficiency value for the first core based at least in part on the first maximum operating point for the first core and a second efficiency value for the at least one second core based at least in part on the second maximum operating point for the at least one second core; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value. Other embodiments are described and claimed.
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