Threshold logic gate
    2.
    发明授权
    Threshold logic gate 失效
    阈值逻辑门

    公开(公告)号:US3597626A

    公开(公告)日:1971-08-03

    申请号:US3597626D

    申请日:1969-04-01

    Inventor: HEIGHTLEY JOHN D

    CPC classification number: H03K17/302 H03K19/0813 H03K19/09441

    Abstract: The dichotomy presented in threshold logic gates by the desirability of a large gap or unit step near the threshold point, coupled with the desirability of a small overall signal swing on the threshold element for a large fan-in, is minimized by replacing the usual linear summing resistor with a nonlinear variable impedance element, such as a field effect transistor in one illustrative embodiment, having a low impedance below the gate threshold and a high impedance in the gap.

    Shift register employing two-phase coupling and transient storage between stages
    3.
    发明授权
    Shift register employing two-phase coupling and transient storage between stages 失效
    移动寄存器采用两相耦合和阶段之间的瞬态存储

    公开(公告)号:US3614469A

    公开(公告)日:1971-10-19

    申请号:US3614469D

    申请日:1969-07-25

    Inventor: HEIGHTLEY JOHN D

    CPC classification number: G11C19/28

    Abstract: In shift registers there is generally provided an intermediate storage function between stages to enable each stage to transfer its information prior to accepting the next incoming signal, i.e., to avoid a race condition. In accordance with this invention there is provided between each stage a coupling circuit comprising in series a Schottky-barrier (SB) diode, an emitterfollower transistor, and a second diode. While the stages are in the holding mode, the state of stage N is coupled through the SB diode, stored on the capacitance at the base of the emitterfollower, and isolated from stage N+1 by the second diode. Upon application of a shift signal, the SB diode immediately turns off and thereby isolates the Nth stage from the emitter-follower. The second diode turns on; and the signal which was stored at the base of the emitter-follower is coupled through the second diode to set the state of stage N+1.

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