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公开(公告)号：US20210358381A1
公开(公告)日：2021-11-18
申请号：US16336546
申请日：2018-08-14
发明人： Zhichong WANG , Haoliang ZHENG , Seungwoo HAN , Guangliang SHANG , Lijun YUAN , Xing YAO , Mingfu HAN
IPC分类号： G09G3/20
摘要： Disclosed is a shift register unit, including a first input circuit, an input control circuit, a pull-down control circuit, a pull-down circuit, an output circuit and a second input circuit. The first input circuit includes a first input sub-circuit, and is configured to, under control of the first signal input terminal, cause a voltage of the first voltage terminal to be output to a second terminal of the first input sub-circuit and output to the pull-up node via a first terminal thereof. The input control circuit is configured to pull down a potential of the second terminal to the potential of a first power supply voltage terminal under control of an enable signal terminal.
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公开(公告)号：US20210225312A1
公开(公告)日：2021-07-22
申请号：US16307060
申请日：2018-06-07
发明人： Mingfu HAN , Guangliang SHANG , Seung Woo HAN , Xing YAO , Haoliang ZHENG , Lijun YUAN , Zhichong WANG
摘要： A shift register unit and a drive method thereof, a gate driving circuit and a display device are provided. The shift register unit includes an input circuit, a pull-up node reset circuit, an output circuit and a coupling circuit. The input circuit is configured to charge a pull-up node in response to an input signal; the pull-up node reset circuit is configured to reset the pull-up node in response to a reset signal; the output circuit is configured to output a first clock signal to a first output terminal under control of a level of the pull-up node; and the coupling circuit is configured to control, by coupling, a potential of the pull-up node in response to a second clock signal.
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3.发明申请公开(公告)号：US20200227006A1
公开(公告)日：2020-07-16
申请号：US16633026
申请日：2019-05-28
发明人： Xing YAO , Mingfu HAN , Guangliang SHANG , Hao ZHU , Yifang CHU , Yunsik IM
摘要： The present disclosure provides a compensation method, compensation device, and a display device. The compensation method includes: adjusting charging time for multiple areas of the display screen so that the charging time for each area is positively related to a distance from the area to a data voltage input terminal; comparing a first grayscale value before compensation of a sub-pixel in an i-th row and j-th column with a second grayscale value input to a sub-pixel in an (i−1)-th row and j-th column; searching a corresponding grayscale compensation parameter from a grayscale compensation parameter table according to the first grayscale value and the second grayscale value; compensating the first grayscale value by the grayscale compensation parameter to obtain a third grayscale value; and inputting the third grayscale value to the sub-pixel in the i-th row and j-th column for display.
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公开(公告)号：US20180293956A1
公开(公告)日：2018-10-11
申请号：US15840757
申请日：2017-12-13
发明人： Xing YAO , Seung-Woo HAN , Guangliang SHANG , Mingfu HAN , Haoliang ZHENG , Yun-Sik IM
摘要： The present disclosure relates to an array substrate, a display panel and a display device. The array substrate includes a plurality of shift register units, a plurality of gate lines and a plurality of data lines crossing the plurality of gate lines. The plurality of gate lines crossing the plurality of data lines defines a plurality of pixel regions. Each of the pixel regions is divided into a driving zone and a pixel unit zone. A plurality of the driving zones in a same column constitute at least one unit region and each of the shift register units is disposed in one of the unit regions to provide scanning signals to the gate line connected thereto.
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公开(公告)号：US20170270879A1
公开(公告)日：2017-09-21
申请号：US15501265
申请日：2016-07-01
发明人： Mingfu HAN , Seungwoo HAN , Guangliang SHANG , Hyunsic CHOI , Xing YAO , Haoliang ZHENG , Xue DONG , Jungmok JUN , Yunsik IM
CPC分类号： G09G3/3648 , G09G3/3677 , G09G2300/0408 , G09G2300/0426 , G09G2310/0286 , G09G2310/08 , G11C19/28
摘要： The present disclosure provides a shift register, including: an input unit, an output control unit, a first pull-down unit, a second pull-down unit, a reset unit, and a pull-down control unit. The input unit comprises a control terminal connected to a signal input terminal, a first terminal connected to a first voltage terminal, and a second terminal connected to a first node. The output control unit comprises a control terminal connected to the first node, a first terminal connected to a first clock signal terminal, and a second terminal connected to a signal output terminal. The first pull-down unit comprises a control terminal connected to a second node, a first terminal connected to the first node, and a second terminal connected to a compensation signal terminal. The second pull-down unit comprises a control terminal connected to the compensation signal terminal, and a first terminal connected to the second node.
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6.发明申请公开(公告)号：US20190180834A1
公开(公告)日：2019-06-13
申请号：US16138878
申请日：2018-09-21
发明人： Lijun YUAN , Mingfu HAN , Seung Woo HAN , Xing YAO , Zhichong WANG , Guangliang SHANG , Haoliang ZHENG
IPC分类号： G11C19/28 , G09G3/3258
摘要： Embodiments of the present application provide a shift register unit, a method for driving the same, a gate driving circuit, and a display apparatus. The shift register unit comprises at least two sub-circuits of a first output sub-circuit, a second output sub-circuit, and a third output sub-circuit. The first output sub-circuit is configured to output a voltage at a signal output terminal to a reset signal output terminal; the second output sub-circuit is configured to output the voltage at the signal output terminal to a gating signal output terminal; and the third output sub-circuit is configured to output a voltage at a second voltage terminal to a light-emitting control signal output terminal or is configured to output a voltage at a first voltage terminal to the light-emitting control signal output terminal.
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公开(公告)号：US20190108809A1
公开(公告)日：2019-04-11
申请号：US16149432
申请日：2018-10-02
发明人： Haoliang ZHENG , Seungwoo HAN , Guangliang SHANG , Xing YAO , Lijun YUAN , Zhichong WANG , Mingfu HAN , Yinglong HUANG
摘要： A shift register, a gate drive circuit, a display apparatus and a driving method of the shift register are provided. The shift register includes an input subcircuit, a first and a second output subcircuits, a trigger signal input terminal, a first and a second signal output terminals, a first and a second clock terminals and a pull-up node, a control terminal and an output terminal of the input subcircuit are electrically coupled to the trigger signal input terminal and the pull-up node, respectively, for providing a valid signal received by the control terminal of the input subcircuit to the pull-up node. The shift register is provided with the first and second output subcircuits which share the same input subcircuit, greatly reducing the number of devices and thus greatly simplifying the structure of the cascaded shift registers and reducing the area of the whole display apparatus.
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公开(公告)号：US20180233210A1
公开(公告)日：2018-08-16
申请号：US15503830
申请日：2016-08-25
发明人： Mingfu HAN , Guangliang SHANG , Yuanbo ZHANG , Yujie GAO , Yan YAN , Yingmeng MIAO , Seungwoo HAN , Zhihe JIN , Xing YAO , Haoliang ZHENG
CPC分类号： G11C19/287 , G09G3/20 , G09G2300/0426 , G09G2310/0245 , G09G2310/0267 , G09G2310/0286 , G11C19/28
摘要： A supplement resetting module for a gate driver circuit, including a pull-up control unit, a pull-down control unit, a clock signal input end, a predetermined level input end, a first control signal input end, a second control signal input end and a signal output end. A control end of the pull-up control unit is connected to the clock signal input end, an output end of the pull-up control unit is connected to the signal output end, a first control end of the pull-down control unit is connected to the first control signal input end, a second control end of the pull-down control unit is connected to the second control signal input end, an input end of the pull-down control unit is connected to the predetermined level input end, and an output end of the pull-down control unit is connected to the signal output end.
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9.发明申请公开(公告)号：US20180188562A1
公开(公告)日：2018-07-05
申请号：US15794298
申请日：2017-10-26
发明人： Zhihe JIN , Seungwoo HAN , Mingfu HAN , Xing YAO , Guangliang SHANG , Zhichong WANG , Lijun YUAN , Haoliang ZHENG , Yunsik IM
IPC分类号： G02F1/1335 , G02F1/1343 , G02F1/133
CPC分类号： G02F1/1336 , G02F1/13306 , G02F1/133553 , G02F1/134309 , G02F1/13439 , G02F1/19 , G02F2001/133616 , G02F2001/133618 , G02F2201/12 , G02F2202/10 , G02F2202/101 , G02F2203/02
摘要： The present application discloses a reflective display panel, a driving method thereof, a control method of a pixel unit and a reflective display device. The reflective display panel comprises: a base substrate, a reflective layer, first and second electrode layers, wherein the first electrode layer is on a side of the reflective layer distal to the base substrate, the second electrode layer is on a side of the first electrode layer distal to the base substrate and insulated from the first electrode layer, materials of the first and second electrode layers are each an electro-optic material, and orthogonal projections of the second and first electrode layers on the base substrate have overlapping areas corresponding to the pixel units.
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公开(公告)号：US20180047329A1
公开(公告)日：2018-02-15
申请号：US15539220
申请日：2016-11-01
发明人： Guangliang SHANG , Seungwoo HAN , Haoliang ZHENG , Xing YAO , Mingfu HAN , Hyunsic CHOI , Yunsik IM , Yinglong HUANG , Jungmok JUN , Xue DONG
CPC分类号： G11C19/287 , G09G3/2096 , G09G3/36 , G09G3/3666 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2320/0223 , G11C5/063 , G11C19/28
摘要： The present disclosure provides a shift register circuit, an array substrate, and a display device. For a first driver and a second driver adjacent to each other in a direction substantially perpendicular to the gate line, a first driving input wiring of the first driver is arranged to input a first clock driving signal to individual shift registers successively from a shift register at a first end position of the first driver to a shift register at a second end position of the first driver, and a second driving input wiring of the second driver is arranged to input a second clock driving signal to individual shift registers successively from a shift register at a second end position of the second driver to a shift register at a first end position of the second driver.
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