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公开(公告)号：US10459271B2
公开(公告)日：2019-10-29
申请号：US15116199
申请日：2016-02-22
Inventor： Jian Guo
IPC: G02F1/1333 , G02F1/136 , G03F7/40 , H01L21/78 , H01L27/12 , G02F1/1362 , H01L21/77
Abstract: The present application discloses a mother substrate comprising a first region comprising a plurality of display substrate units; and a second region; the first region comprises a buffer layer on and in contact with a base substrate, the second region comprises a mat layer on and in contact with the base substrate for reducing segment difference between the first region and the second region.
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公开(公告)号：US10204936B2
公开(公告)日：2019-02-12
申请号：US14405008
申请日：2013-11-20
Inventor： Tiansheng Li , Jian Guo , Zhenyu Xie
Abstract: An array substrate includes a display region and a Gate driver On Array (GOA) region. In the GOA region, a gate metal electrode, a gate insulating layer, an active layer, a transition layer, and a source-drain metal electrode are formed in sequence from bottom to top, and a via hole is provided penetrating the transition layer, the active layer and the gate insulating layer, the source-drain metal electrode is electrically connected to the gate metal electrode through the via hole; and at an edge of the via hole, there is formed an angle opening upward at edges of the transition layer and the active layer. There are further disclosed a manufacturing method of the array substrate and a display device provided with the array substrate.
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公开(公告)号：US09929183B2
公开(公告)日：2018-03-27
申请号：US14387504
申请日：2013-06-09
Inventor： Jian Guo
IPC: H01L27/12
CPC classification number: H01L27/124 , H01L27/1259 , H01L27/127
Abstract: Embodiments of the present invention disclose an array substrate, a manufacturing method of the array substrate and a display device, and the manufacturing method of the array substrate comprises: forming a gate line and a gate electrode on a base substrate; forming a gate insulating layer above the gate line and the gate electrode; successively depositing a semiconductor layer and a metal layer above the gate insulating layer, and forming an active layer, a source electrode and a drain electrode that are disposed above the gate electrode and a residual semiconductor layer disposed above the gate line and a signal line covering the residual semiconductor layer by using one patterning process; performing a patterning process for the signal line, the residual semiconductor layer disposed below the signal line and the gate insulating layer to form a via hole, so that a surface of the gate line, side sectional surfaces of the signal line, side sectional surfaces of the residual semiconductor layer and side sectional surfaces of the gate insulating layer are exposed through the via hole; and forming a lapping conductive layer at a position where the via hole is located, so that the signal line and the gate line are electrically connected.
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公开(公告)号：US09893098B2
公开(公告)日：2018-02-13
申请号：US15262523
申请日：2016-09-12
Inventor： Jian Guo
IPC: H01L27/12 , G02F1/1368 , H01L27/32
CPC classification number: H01L27/1288 , G02F1/1368 , G02F2201/121 , G02F2201/123 , G02F2201/124 , H01L27/124 , H01L27/3276
Abstract: Embodiments of the present disclosure provide an array substrate and a fabrication method thereof, and a display device. The fabrication method of the array substrate includes: forming a gate metal layer, a gate insulating layer, an active layer and a source-drain metal layer on a base substrate. The forming the gate insulating layer, the active layer and the source-drain metal layer on the base substrate comprises: forming a gate insulating film, an active layer film and a source-drain metal film on the base substrate; forming the gate insulating layer, the active layer and the source-drain metal layer by a single patterning process. The number of the exposing process is reduced, the production cycle is shortened and the fabrication cost is reduced.
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公开(公告)号：US09799683B2
公开(公告)日：2017-10-24
申请号：US15098914
申请日：2016-04-14
Inventor： Xuecheng Hou , Kai Lu , Jian Guo
CPC classification number: H01L27/1248 , H01L27/124 , H01L27/1244 , H01L27/1259
Abstract: The present invention provides an array substrate, a preparation method thereof and a display device. The array substrate includes at least one thin film transistor and a resin layer having at least one resin via hole, wherein a film-thickness-difference-adjusting layer used for reducing the film thickness difference at the resin via hole is arranged at the lower part of the resin layer in at least a part of the resin via hole. By providing the film-thickness-difference-adjusting layer, the film thickness difference at the resin via hole can be effectively reduced, and when a photolithographic process is performed, the difference of the thickness of the photoresist here and the thicknesses at other positions is reduced, so that the via hole fluctuation of a passivation layer caused by the larger film thickness difference at the resin via hole is improved, and the metal residue problem of the pixel electrodes is effectively avoided.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20170192294A1
公开(公告)日：2017-07-06
申请号：US15116199
申请日：2016-02-22
Inventor： Jian Guo
IPC: G02F1/1333 , H01L21/78 , G03F7/40
CPC classification number: G02F1/133351 , G02F1/136 , G02F1/1362 , G02F2201/07 , G03F7/40 , H01L21/78 , H01L27/1218 , H01L2021/775
Abstract: The present application discloses a mother substrate comprising a first region comprising a plurality of display substrate units; and a second region; the first region comprises a buffer layer on and in contact with a base substrate, the second region comprises a mat layer on and in contact with the base substrate for reducing segment difference between the first region and the second region.
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公开(公告)号：US09547195B2
公开(公告)日：2017-01-17
申请号：US14360523
申请日：2013-10-10
Inventor： Renwei Guo , Xue Dong , Jian Guo
IPC: G02F1/1335 , G02F1/13363 , G02F1/1343 , G02F1/1368 , G02F1/1362
CPC classification number: G02F1/133617 , B82Y30/00 , C09K11/565 , G02B5/201 , G02F1/133514 , G02F1/13363 , G02F1/134336 , G02F1/1362 , G02F1/1368 , G02F2001/133357 , G02F2001/133565 , G02F2001/133614 , G02F2001/133638 , G02F2001/136222 , G02F2201/086 , G02F2202/108 , G02F2202/36 , G02F2203/01
Abstract: A liquid crystal display (LCD) and a display device are disclosed. The LCD is provided with a plurality of pixel units; each pixel unit includes a plurality of sub-pixel units for displaying different colors; quantum dot (QD) layers capable of allowing backlight to run through are disposed at positions of an array substrate, corresponding to the sub-pixel units of at least one color of the pixel units; the QD layers are excited by ultraviolet light in sunlight and emit light which at least is of the color of the sub-pixel units; and color filters are disposed between the QD layers and the opposing substrate. The LCD has enhanced display brightness and higher outdoor viewability in the case of outdoor display.
Abstract translation: 公开了一种液晶显示器（LCD）和显示装置。 LCD设置有多个像素单元; 每个像素单元包括用于显示不同颜色的多个子像素单元; 能够使背光源穿过的量子点（QD）层配置在与像素单元的至少一种颜色的子像素单元相对应的阵列基板的位置; QD层被太阳光中的紫外线激发，并发出至少具有子像素单元的颜色的光; 并且滤色器设置在QD层和相对基板之间。 在室外显示的情况下，LCD具有增强的显示亮度和更高的户外可见度。
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8.发明申请ARRAY SUBSTRATE, DISPLAY DEVICE HAVING THE SAME, AND FABRICATING METHOD THEREOF 有权阵列基板，具有该基板的显示装置及其制造方法公开(公告)号：US20170005117A1
公开(公告)日：2017-01-05
申请号：US15030596
申请日：2015-12-28
Inventor： Jian Guo
IPC: H01L27/12
CPC classification number: H01L27/1248 , G02F1/136227 , H01L27/1259 , H01L29/41733
Abstract: The present application discloses a method of fabricating an array substrate comprising forming a via extending through a first insulating layer and a second insulating layer, the via comprising a first sub-via in the first insulating layer and the second sub-via in a second insulating layer; mobilizing a portion of first insulating layer material surrounding the first sub-via; and distributing the mobilized portion of the first insulating layer material over a sidewall of the second sub-via.
Abstract translation: 本申请公开了一种制造阵列基板的方法，包括形成延伸穿过第一绝缘层和第二绝缘层的通孔，所述通孔包括在第一绝缘层中的第一子通孔和在第二绝缘层中的第二子通孔 层; 移动围绕所述第一子通路的第一绝缘层材料的一部分; 以及将第一绝缘层材料的动员部分分布在第二子通孔的侧壁上。
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公开(公告)号：US09348161B2
公开(公告)日：2016-05-24
申请号：US14428932
申请日：2014-07-10
IPC: H01L35/24 , H01L25/16 , H01L27/00 , G02F1/1368 , G02F1/133 , H01L27/12 , G02F1/13 , G02F1/1335 , G02F1/1343 , G02F1/1333
CPC classification number: G02F1/13318 , G02F1/1313 , G02F1/133555 , G02F1/134309 , G02F1/13439 , G02F1/1368 , G02F2001/13324 , G02F2001/133357 , G02F2001/134345 , H01L25/167 , H01L27/12 , H01L2924/0002 , H01L2924/00
Abstract: An array substrate, a liquid crystal display panel and a display device are disclosed. The array substrate includes a base substrate, a plurality of pixel units disposed on the base substrate, a drive module providing each of the pixel units with a display signal; a photovoltaic battery component electrically connected to the drive module, which includes a plurality of photovoltaic sub-batteries, each of the photovoltaic sub-batteries including a first transparent electrode, a photovoltaic thin film and a second transparent electrode; the orthographic projection of the photovoltaic thin film on the base substrate lies within the light blocking region. Because the orthographic projection of the photovoltaic thin film on the base substrate lies within the light blocking region, aperture ratio of each pixel unit in the array substrate will not be affected.
Abstract translation: 公开了阵列基板，液晶显示面板和显示装置。 阵列基板包括基底基板，设置在基底基板上的多个像素单元，为每个像素单元提供显示信号的驱动模块; 电连接到驱动模块的光伏电池组件，其包括多个光伏子电池，每个光伏子电池包括第一透明电极，光伏薄膜和第二透明电极; 光电薄膜在基底基板上的正投影位于遮光区域内。 由于基底基板上的光电薄膜的正投影位于遮光区域内，阵列基板中的各像素单元的开口率将不受影响。
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公开(公告)号：US20150303225A1
公开(公告)日：2015-10-22
申请号：US14439999
申请日：2014-09-05
Inventor： Xiaohui Jiang , Jian Guo , Tiansheng Li
IPC: H01L27/12 , G02F1/1362 , G02F1/1368
CPC classification number: H01L27/1262 , G02F1/136286 , G02F1/1368 , G02F2001/136295 , H01L27/124 , H01L27/1288 , H01L29/66765
Abstract: An array substrate and a fabrication method thereof and a display device are provided. The fabrication method comprises: preparing a base substrate, the base substrate including a pixel region and a gate on array region; forming a pattern including a gate electrode and a pattern of an active layer on the base substrate, and forming a gate lead on the gate on array region, by a first patterning process; forming a pattern of a gate insulating layer by a second patterning process; forming a pattern including a source/drain electrode by a third patterning process; forming a pattern of a planarization layer by a fourth patterning layer; and forming a pattern including a pixel electrode by a fifth patterning layer.
Abstract translation: 提供阵列基板及其制造方法和显示装置。 所述制造方法包括：准备基底基板，所述基底基板包括像素区域和阵列区域上的栅极; 在基底基板上形成包括栅电极和有源层图形的图案，并通过第一图案化工艺在阵列区上的栅极上形成栅极引线; 通过第二图案化工艺形成栅极绝缘层的图案; 通过第三图案化工艺形成包括源极/漏极的图案; 通过第四图案形成层形成平坦化层的图案; 以及通过第五图案形成层形成包括像素电极的图案。
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