ARRAY SUBSTRATE AND FABRICATING METHOD THEREOF, DISPLAY PANEL AND DISPLAY DEVICE

    公开(公告)号:US20200035716A1

    公开(公告)日:2020-01-30

    申请号:US16396726

    申请日:2019-04-28

    IPC分类号: H01L27/12

    摘要: The present disclosure is in the field of display technologies, and provides an array substrate including an IGZO film layer, a gate layer, and a gate insulating layer. The gate layer is provided with broken lines at a position thereof overlapping the IGZO film layer to form a first gate line and a second gate line. The gate insulating layer is disposed between the IGZO film layer and the gate layer, and is provided with at least two through holes thereon, in which the first gate line is connected with the IGZO film layer through one of the through holes, and the second gate line is connected with the IGZO film layer through another through hole, thus, connecting the IGZO film layer in series into the gate layer.

    DISPLAY SUBSTRATE, METHOD FOR FABRICATING THE SAME, AND DISPLAY PANEL

    公开(公告)号:US20200219959A1

    公开(公告)日:2020-07-09

    申请号:US16711667

    申请日:2019-12-12

    IPC分类号: H01L27/32 H01L51/52

    摘要: A display substrate, a method for fabricating the same, and a display panel are provided. The display substrate includes: a substrate, and a first conductive layer, at least two insulation layers, and a second conductive layer, the second conductive layer being electrically connected with the first conductive layer through via-holes, and the at least two insulation layers including a first insulation layer in contact with the first conductive layer, wherein the display substrate further includes an assisting alignment structure on the surface of the first insulation layer, and the orthographic projection of the assisting alignment structure surrounds at least part of the edge of the orthographic projection of the first via-hole in the first insulation layer on the substrate, so that the orthographic projection of the first via-hole on the first conductive layer lies within the pattern of the first conductive layer.

    THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME, ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME, AND DISPLAY DEVICE
    5.
    发明申请
    THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME, ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME, AND DISPLAY DEVICE 有权
    薄膜晶体管及其制造方法,阵列基板及其制造方法以及显示装置

    公开(公告)号:US20150340455A1

    公开(公告)日:2015-11-26

    申请号:US14376028

    申请日:2013-11-27

    摘要: The present invention provides a thin film transistor and a method of fabricating the thin film transistor, an array substrate and a method of fabricating the array substrate, and a display device. The thin film transistor includes a substrate and a gate, an insulation layer, an active layer, a source and a drain which are provided on the substrate. A spacer layer is also provided between the gate and the active layer, and the spacer layer overlaps at least with one of the gate and the active layer having a smaller area in an orthographic projection direction. The spacer layer can effectively prevent material forming the gate from being diffused into the active layer, thereby ensuring stability of performance of the thin film transistor. In the array substrate utilizing the thin film transistor, the spacer layer further extends to a region corresponding to a gate line.

    摘要翻译: 本发明提供一种薄膜晶体管和制造薄膜晶体管的方法,阵列基板和制造阵列基板的方法以及显示装置。 薄膜晶体管包括设置在基板上的基板和栅极,绝缘层,有源层,源极和漏极。 间隔层还设置在栅极和有源层之间,并且间隔层至少与栅极和有源层中的一个重叠,在正投影方向上具有较小的面积。 间隔层可以有效地防止形成栅极的材料扩散到有源层中,从而确保薄膜晶体管的性能的稳定性。 在利用薄膜晶体管的阵列基板中,间隔层进一步延伸到对应于栅极线的区域。

    ARRAY SUBSTRATE, PREPARATION METHOD THEREFOR, AND DISPLAY DEVICE

    公开(公告)号:US20210296406A1

    公开(公告)日:2021-09-23

    申请号:US17264283

    申请日:2020-05-12

    IPC分类号: H01L27/32 H01L51/56 H01L51/52

    摘要: The present disclosure relates to the technical field of display, and discloses an array substrate, a preparation method therefor, and a display device. When dielectric layers, such as a buffer layer, an interlayer dielectric layer, and a gate insulation layer, are formed between a source-drain electrode and a substrate, the thickness of at least one dielectric layer among said dielectric layers underneath a first through hole for connecting a drain electrode and an anode is increased, which is to say that the drain electrode is raised to be further away from the substrate, causing the drain electrode to be closer to a surface of a planarization layer that faces away from the substrate, i.e., reducing the thickness of a portion of the planarization layer above the drain electrode.

    DRIVE BACKPLANE AND DISPLAY PANEL
    9.
    发明公开

    公开(公告)号:US20240365608A1

    公开(公告)日:2024-10-31

    申请号:US18028944

    申请日:2022-06-24

    IPC分类号: H10K59/131 H10K59/121

    CPC分类号: H10K59/131 H10K59/1216

    摘要: Provided is drive backplane. The drive backplane includes: a substrate, including a plurality of light transmitting regions and a plurality of sub-pixel regions; a pixel drive circuit and an anode block that are disposed in the sub-pixel region, the pixel drive circuit being electrically connected to the anode block; and repair lines and repair electrodes that are disposed in the light transmitting regions, an end of the repair line being spaced from the repair electrode; wherein, an end, departing from the repair electrode, of the repair line is electrically connected to the anode block in a first sub-pixel region, the repair electrode is electrically connected to the anode block in a second sub-pixel region.