公开(公告)号：US06664585B2

公开(公告)日：2003-12-16

申请号：US10012563

申请日：2001-12-12

申请人： Beom-jun Jin ,  Byeong-yun Nam

发明人： Beom-jun Jin ,  Byeong-yun Nam

IPC分类号： H01L27108

CPC分类号： H01L27/10855 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/10885 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes a bit line stack and a storage node contact hole which are aligned at bit line spacers formed at both side walls of the bit line stack and exposes a pad. The semiconductor memory device includes a multi-layered storage node contact plug in which a first storage node contact plug and a second storage node contact plug are sequentially formed. The first storage node contact plug is formed of titanium nitride and the second storage node contact plug is formed of polysilicon. An ohmic layer may be formed on the pad and under the first storage node contact plug. A barrier metal layer, which acts as a third storage node contact plug, may be formed on the second storage node contact plug.

公开(公告)号：US07009257B2

公开(公告)日：2006-03-07

申请号：US10741751

申请日：2003-12-19

申请人： Young-pil Kim ,  Beom-jun Jin ,  Hyoung-joon Kim ,  Byeong-yun Nam

发明人： Young-pil Kim ,  Beom-jun Jin ,  Hyoung-joon Kim ,  Byeong-yun Nam

IPC分类号： H01L29/72

CPC分类号： H01L21/76897 ,  H01L21/28525 ,  H01L21/76895 ,  H01L21/823425 ,  H01L21/823475

摘要： An integrated circuit device includes a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain region. A lower pad layer is disposed on the source region and/or the drain region and comprises a same crystalline structure as the substrate. A conductive layer is disposed on the lower pad layer such that at least a portion of the conductive layer is disposed between the lower pad layer and the gate pattern. An insulating layer is disposed between the gate pattern and both the lower pad layer and the conductive layer, and also between the conductive layer and the substrate.

公开(公告)号：US06576963B2

公开(公告)日：2003-06-10

申请号：US09992069

申请日：2001-11-14

申请人： Beom-jun Jin ,  Byeong-yun Nam ,  Young-pil Kim

发明人： Beom-jun Jin ,  Byeong-yun Nam ,  Young-pil Kim

IPC分类号： H01L2976

CPC分类号： H01L21/76897 ,  H01L21/823475 ,  H01L29/6653 ,  Y10S257/90

摘要： A method of forming self-aligned contact holes exposing source/drain regions in a semiconductor substrate using only etch mask layers is provided. In the method, sacrificial spacers are formed of a material having an excellent etching selectivity to the etch mask layers at sidewalls of gate electrodes in a cell area. Also, an interlevel dielectric layer is formed of a material having an excellent etching selectivity to the etch mask layers. The sacrificial spacers are removed when forming the self-aligned contact holes. Dielectric spacers are formed of a material having a low dielectric constant, without considering its etching selectivity to the interlevel dielectric layer. Thus, a reduction in the operational speed of a semiconductor device having transistors can be prevented.

摘要翻译： 提供了一种使用仅使用蚀刻掩模层在半导体衬底中暴露源/漏区的自对准接触孔的方法。 在该方法中，牺牲隔离物由对单元区域中的栅电极的侧壁处的蚀刻掩模层具有优良蚀刻选择性的材料形成。 此外，层间介电层由对蚀刻掩模层具有优异蚀刻选择性的材料形成。 当形成自对准的接触孔时，去除牺牲隔离物。 电介质间隔物由具有低介电常数的材料形成，而不考虑其对层间电介质层的蚀刻选择性。 因此，可以防止具有晶体管的半导体器件的操作速度的降低。

公开(公告)号：US07060575B2

公开(公告)日：2006-06-13

申请号：US10426585

申请日：2003-04-30

申请人： Beom-jun Jin ,  Byeong-yun Nam ,  Young-pil Kim

发明人： Beom-jun Jin ,  Byeong-yun Nam ,  Young-pil Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/76897 ,  H01L21/823475 ,  H01L29/6653 ,  Y10S257/90

摘要： A method of forming self-aligned contact holes exposing source/drain regions in a semiconductor substrate using only etch mask layers is provided. In the method, sacrificial spacers are formed of a material having an excellent etching selectivity to the etch mask layers at sidewalls of gate electrodes in a cell area. Also, an interlevel dielectric layer is formed of a material having an excellent etching selectivity to the etch mask layers. The sacrificial spacers are removed when forming the self-aligned contact holes. Dielectric spacers are formed of a material having a low dielectric constant, without considering its etching selectivity to the interlevel dielectric layer. Thus, a reduction in the operational speed of a semiconductor device having transistors can be prevented.

公开(公告)号：US06984568B2

公开(公告)日：2006-01-10

申请号：US10685569

申请日：2003-10-16

申请人： Beom-jun Jin ,  Byeong-yun Nam

发明人： Beom-jun Jin ,  Byeong-yun Nam

IPC分类号： H01L21/20

CPC分类号： H01L27/10855 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/10885 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes a bit line stack and a storage node contact hole which are aligned at bit line spacers formed at both side walls of the bit line stack and exposes a pad. The semiconductor memory device includes a multi-layered storage node contact plug in which a first storage node contact plug and a second storage node contact plug are sequentially formed. The first storage node contact plug is formed of titanium nitride and the second storage node contact plug is formed of polysilicon. An ohmic layer may be formed on the pad and under the first storage node contact plug. A barrier metal layer, which acts as a third storage node contact plug, may be formed on the second storage node contact plug.

摘要翻译： 半导体存储器件包括位线堆叠和存储节点接触孔，它们位于形成在位线堆叠的两个侧壁处的位线间隔件处并且暴露焊盘。 半导体存储器件包括多层存储节点接触插头，其中依次形成第一存储节点接触插头和第二存储节点接触插头。 第一存储节点接触插塞由氮化钛形成，第二存储节点接触插塞由多晶硅形成。 可以在焊盘上和第一存储节点接触插头下方形成欧姆层。 作为第三存储节点接触插头的阻挡金属层可以形成在第二存储节点接触插头上。

公开(公告)号：US06689654B2

公开(公告)日：2004-02-10

申请号：US10038967

申请日：2002-01-04

申请人： Young-pil Kim ,  Beom-jun Jin ,  Hyoung-joon Kim ,  Byeong-yun Nam

发明人： Young-pil Kim ,  Beom-jun Jin ,  Hyoung-joon Kim ,  Byeong-yun Nam

IPC分类号： H01L218238

CPC分类号： H01L21/76897 ,  H01L21/28525 ,  H01L21/76895 ,  H01L21/823425 ,  H01L21/823475

摘要： An integrated circuit device includes a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain region. A lower pad layer is disposed on the source region and/or the drain region and comprises a same crystalline structure as the substrate. A conductive layer is disposed on the lower pad layer such that at least a portion of the conductive layer is disposed between the lower pad layer and the gate pattern. An insulating layer is disposed between the gate pattern and both the lower pad layer and the conductive layer, and also between the conductive layer and the substrate.

摘要翻译： 集成电路器件包括其中形成有源极区和漏极区的衬底。 在源极区域和漏极区域之间的衬底上设置栅极图案。 下焊盘层设置在源极区域和/或漏极区域上并且包括与衬底相同的晶体结构。 导电层设置在下焊盘层上，使得导电层的至少一部分设置在下焊盘层和栅极图案之间。 绝缘层设置在栅极图案与下焊盘层和导电层之间以及导电层和基板之间。

公开(公告)号：US06885052B2

公开(公告)日：2005-04-26

申请号：US09790240

申请日：2001-02-21

申请人： Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

发明人： Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

IPC分类号： H01L27/10 ,  H01L21/60 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10888

摘要： A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided. The semiconductor memory device having self-aligned contacts includes a plurality of gate electrode patterns arranged in parallel on a semiconductor substrate, in which a plurality of first spacers are formed along the sidewalls of the gate electrode patterns, a first interdielectric layer formed on the entire surface of a resultant in which the first spacers are formed, a plurality of bit line patterns arranged in parallel on the first interdielectric layer to be perpendicular to the gate electrode patterns, in which a plurality of second spacers are formed along the sidewalls of the bit line patterns, a plurality of contacts for bit lines self-aligned with the first spacers, a second interdielectric layer formed on the entire surface of a resultant in which the second spacers are formed, and a plurality of contacts for storage electrodes simultaneously self-aligned with the second and first spacers.

摘要翻译： 一种具有自对准触点的半导体存储器件及其制造方法，其特征在于能够防止位线触点和存储电极触点之间的短路，并提高加工余量。 具有自对准触点的半导体存储器件包括平行布置在半导体衬底上的多个栅电极图案，其中多个第一间隔物沿着栅电极图案的侧壁形成，第一绝缘层整体形成 其中形成有第一间隔物的结果的表面，在第一电介质层上平行布置成垂直于栅极电极图案的多个位线图案，其中沿着该位的侧壁形成多个第二间隔物 线图案，用于与第一间隔物自对准的位线的多个触点，形成在其中形成有第二间隔物的结果的整个表面上的第二电介质层和用于存储电极的多个触点同时自对准 与第二和第一间隔物。

公开(公告)号：US06429107B2

公开(公告)日：2002-08-06

申请号：US09839855

申请日：2001-04-20

申请人： Hyoung-joon Kim ,  Byeong-yun Nam ,  Kyung-won Park

发明人： Hyoung-joon Kim ,  Byeong-yun Nam ,  Kyung-won Park

IPC分类号： H01L213205

CPC分类号： H01L21/76897 ,  H01L21/76801

摘要： A method for forming a conductive contact of a semiconductor device is provided. According to one aspect of the present invention, a dummy dielectric layer pattern having a dummy opening and an interdielectric layer pattern having a lower etch-rate than that of the dummy dielectric layer, for filling the dummy opening are formed on a semiconductor substrate. The dummy dielectric layer pattern using the interdielectric layer pattern as an etching mask is selectively removed, and a contact opening for exposing the semiconductor substrate of a portion in which the dummy dielectric layer pattern is located.

摘要翻译： 提供一种用于形成半导体器件的导电接触的方法。 根据本发明的一个方面，在半导体衬底上形成有用于填充虚拟开口的具有比虚拟电介质层低的蚀刻速率的虚拟开口和介电层图案的虚拟介电层图案。 选择性地去除使用电介质层图案作为蚀刻掩模的虚拟介电层图案，以及用于使虚设电介质层图案所在的部分露出半导体基板的接触开口。

公开(公告)号：US6004882A

公开(公告)日：1999-12-21

申请号：US16022

申请日：1998-01-30

申请人： Hyoun-woo Kim ,  Byeong-yun Nam ,  Byong-sun Ju ,  Won-jong Yoo

发明人： Hyoun-woo Kim ,  Byeong-yun Nam ,  Byong-sun Ju ,  Won-jong Yoo

IPC分类号： C23F4/00 ,  H01L21/285 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L21/32136 ,  H01L21/28512

摘要： A method for etching a platinum (Pt) layer of a semiconductor device is provided which improves the etching slope of a sidewall of the platinum layer used as a storage node of the semiconductor device. The semiconductor device consists of a semiconductor substrate including a bottom layer on which various other layers are formed. Specifically, according to this invention, a Pt layer is formed on a bottom layer of a semiconductor substrate. An adhesive layer is then formed on the Pt layer while a mask layer is formed on the adhesive layer. After formation of the various layers, the mask layer and adhesive layer are patterned using an etching process to form a mask pattern and an adhesive layer mask pattern, respectively. The semiconductor substrate is then heated and an etching process is performned on the Pt layer using the mask pattern and the adhesive layer mask pattern to form etching slope sidewalls of the Pt layer having etching slopes close to vertical. Accordingly, the Pt electrodes of the semiconductor device of the present invention have a finer pattern than those of the prior art. Finally, overetching is done to remove the mask pattern.

摘要翻译： 提供一种用于蚀刻半导体器件的铂（Pt）层的方法，其改善了用作半导体器件的存储节点的铂层的侧壁的蚀刻斜率。 半导体器件由包括其上形成有各种其它层的底层的半导体衬底组成。 具体地，根据本发明，在半导体衬底的底层上形成Pt层。 然后在Pt层上形成粘合剂层，同时在粘合剂层上形成掩模层。 在形成各层之后，使用蚀刻工艺对掩模层和粘合剂层进行图案化以分别形成掩模图案和粘合剂层掩模图案。 然后加热半导体衬底并使用掩模图案和粘合剂层掩模图案在Pt层上进行蚀刻处理，以形成具有接近垂直的蚀刻斜率的Pt层的蚀刻斜面侧壁。 因此，本发明的半导体器件的Pt电极具有比现有技术更精细的图案。 最后，进行过蚀刻以去除掩模图案。

公开(公告)号：US06187686B1

公开(公告)日：2001-02-13

申请号：US09325171

申请日：1999-06-03

申请人： Hwa-sook Shin ,  Byeong-yun Nam

发明人： Hwa-sook Shin ,  Byeong-yun Nam

IPC分类号： H01L2144

CPC分类号： C23F1/02 ,  C23F4/00 ,  H01L21/0332 ,  H01L21/28061 ,  H01L21/28123 ,  H01L21/32139 ,  H01L29/4941

摘要： A method for forming a patterned platinum layer on a microelectronic substrate includes the steps of forming a platinum layer on the microelectronic substrate, and forming a mask layer on the platinum layer. In particular, the mask layer defines exposed portions of the platinum layer, and the mask layer comprises a mask material including titanium. The exposed portions of the platinum layer are then selectively removed to form the patterned platinum layer. Related structures are also disclosed.

摘要翻译： 在微电子衬底上形成图案化铂层的方法包括在微电子衬底上形成铂层并在铂层上形成掩模层的步骤。 具体地，掩模层限定铂层的曝光部分，掩模层包括包含钛的掩模材料。 然后选择性地去除铂层的暴露部分以形成图案化的铂层。 还公开了相关结构。