公开(公告)号：US05998807A

公开(公告)日：1999-12-07

申请号：US925672

申请日：1997-09-09

申请人： Bernhard Lustig ,  Herbert Schaefer ,  Martin Franosch

发明人： Bernhard Lustig ,  Herbert Schaefer ,  Martin Franosch

IPC分类号： H01L21/8238 ,  H01L21/8256 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L27/092 ,  H01L21/8256 ,  H01L27/1203

摘要： Semiconductor islands respectively comprise at least a Si.sub.1-x Ge.sub.x layer and a distorted silicon layer that exhibits essentially the same lattice constant as the Si.sub.1-x Ge.sub.x layer are formed on an insulating layer that is located on a carrier plate. The semiconductor islands are preferably formed by selective epitaxy and comprise p-channel MOS transistors and/or n-channel MOS transistors.

摘要翻译： 半导体岛分别至少包含Si1-xGex层和在位于载体板上的绝缘层上形成与Si1-xGex层基本相同的晶格常数的失真硅层。 半导体岛优选通过选择性外延形成并且包括p沟道MOS晶体管和/或n沟道MOS晶体管。

公开(公告)号：US6159815A

公开(公告)日：2000-12-12

申请号：US269311

申请日：1999-06-04

申请人： Bernhard Lustig ,  Herbert Schafer ,  Martin Franosch

发明人： Bernhard Lustig ,  Herbert Schafer ,  Martin Franosch

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/66636 ,  H01L21/823864

摘要： In order to produce a MOS transistor with HDD profile and LDD profile, the HDD profile is firstly formed, followed by the LDD profile, in the area for the LDD profile in order to produce steep dopant profiles. The LDD profile is preferably produced by etching and in situ doped selective epitaxy.

摘要翻译： PCT No.PCT / DE97 / 01933 Sec。 371日期1999年6月4日第 102（e）1999年6月4日PCT PCT 1996年9月3日PCT公布。 公开号WO98 / 13865 日期1998年4月2日为了生产具有HDD配置文件和LDD配置文件的MOS晶体管，首先在LDD配置文件的区域中形成HDD配置文件，然后是LDD配置文件，以生成陡峭的掺杂剂配置文件。 LDD分布优选通过蚀刻和原位掺杂的选择性外延生长。

公开(公告)号：US6022786A

公开(公告)日：2000-02-08

申请号：US32484

申请日：1998-02-27

申请人： Martin Franosch ,  Wolfgang Hoenlein ,  Helmut Klose ,  Gerrit Lange ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schaefer ,  Reinhard Stengl ,  Hermann Wendt ,  Dietrich Widmann

发明人： Martin Franosch ,  Wolfgang Hoenlein ,  Helmut Klose ,  Gerrit Lange ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schaefer ,  Reinhard Stengl ,  Hermann Wendt ,  Dietrich Widmann

IPC分类号： H01L21/306 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC分类号： H01L27/10861

摘要： For manufacturing a capacitor, in particular for a dynamic memory cell arrangement, a trench is etched in a substrate. In the trench, a layer sequence is produced that contains, in alternating fashion, layers of doped silicon and germanium-containing layers. By anisotropic etching, the surface of the semiconductor substrate (12) is exposed in the region of the trench floor. The trenches are filled with a conductive support structure (20). The germanium-containing layers are removed selectively to the layers of doped silicon. The exposed surface of the layers of doped silicon (17) and of the support structure (20) are provided with a capacitor dielectric (22), onto which is applied a counter-electrode (23).

摘要翻译： 为了制造电容器，特别是用于动态存储单元布置，在衬底中蚀刻沟槽。 在沟槽中，产生层序列，其交替地包含掺杂的硅和含锗层的层。 通过各向异性蚀刻，半导体衬底（12）的表面暴露在沟槽底板的区域中。 沟槽填充有导电支撑结构（20）。 含锗层被选择性地去除掺杂硅层。 掺杂硅（17）和支撑结构（20）的层的暴露表面设置有电容器电介质（22），其上施加有对电极（23）。

公开(公告)号：US08329532B2

公开(公告)日：2012-12-11

申请号：US13314595

申请日：2011-12-08

申请人： Herbert Schaefer ,  Martin Franosch ,  Thomas Meister ,  Josef Boeck

发明人： Herbert Schaefer ,  Martin Franosch ,  Thomas Meister ,  Josef Boeck

IPC分类号： H01L21/8238

CPC分类号： H01L21/02639 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02661

摘要： One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

公开(公告)号：US20090261327A1

公开(公告)日：2009-10-22

申请号：US12106667

申请日：2008-04-21

申请人： Herbert Schaefer ,  Martin Franosch ,  Thomas Meister ,  Josef Boeck

发明人： Herbert Schaefer ,  Martin Franosch ,  Thomas Meister ,  Josef Boeck

IPC分类号： H01L27/00 ,  H01L21/62

CPC分类号： H01L21/02639 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02661

摘要： One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

摘要翻译： 本发明的一个实施例涉及利用原位差分外延在半导体主体上同时沉积多个不同结晶结构的方法。 在本发明的一个实施方案中，形成制备表面，得到两个不同的结晶区域，单晶硅衬底区域和隔离层区域。 单晶硅层和非晶硅层同时直接分布在单晶硅衬底区域和隔离层区域的制备表面上。 沉积包括形成两个或更多个子层。 可以为每个单独的子层改变工艺参数以优化沉积特性。

公开(公告)号：US07064360B2

公开(公告)日：2006-06-20

申请号：US10470816

申请日：2002-02-04

申请人： Martin Franosch ,  Thomas Meister ,  Herbert Schaefer ,  Reinhard Stengl

发明人： Martin Franosch ,  Thomas Meister ,  Herbert Schaefer ,  Reinhard Stengl

IPC分类号： H01L31/0328

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A method is provided to fabricate a bipolar transistor with a low base connection resistance, low defect density and improved scalability. Scalability is to be understood in this case as both the lateral scaling of the emitter window and the vertical scaling of the base width (low temperature budget). The temperature budget can be kept low in the base region since no implantations are required in order to reduce the base connection resistance. Furthermore, the difficulties associated with the point defects are largely avoided.

摘要翻译： 提供了一种制造具有低基极连接电阻，低缺陷密度和改进的可扩展性的双极晶体管的方法。 在这种情况下可以理解可扩展性，因为发射器窗口的横向缩放和基础宽度（低温预算）的垂直缩放。 由于不需要植入来降低基极连接电阻，所以在基极区域中的温度预算可以保持较低。 此外，很大程度上避免了与点缺陷相关的困难。

公开(公告)号：US5943571A

公开(公告)日：1999-08-24

申请号：US883571

申请日：1997-06-26

申请人： Herbert Schaefer ,  Martin Franosch ,  Reinhard Stengl ,  Volker Lehmann ,  Hans Reisinger ,  Hermann Wendt

发明人： Herbert Schaefer ,  Martin Franosch ,  Reinhard Stengl ,  Volker Lehmann ,  Hans Reisinger ,  Hermann Wendt

IPC分类号： C23C16/04 ,  H01L21/033 ,  H01L21/20 ,  H01L21/205 ,  H01L21/266 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  C23C16/04 ,  H01L21/02381 ,  H01L21/02425 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0334 ,  H01L27/11517 ,  H01L29/66825

摘要： For manufacturing fine structures, nuclei that define the dimensions of the fine structures are formed on the surface of a substrate in a CVD process upon employment of a first process gas that contains SiH.sub.4 and GeH.sub.4 in a carrier gas. The nuclei can be employed both as a mask, for example, when etching or implanting, as will as active or passive component parts that remain in the structure, for example, as charge storages in the dielectric of an EEPROM.

摘要翻译： 为了制造精细结构，使用在载气中使用含有SiH 4和GeH 4的第一工艺气体时，在CVD工艺的基板的表面上形成限定精细结构的尺寸的核。 核可以同时用作掩模，例如蚀刻或注入时，以及保留在结构中的有源或无源部件，例如作为电荷存储在EEPROM的电介质中。

公开(公告)号：US08102052B2

公开(公告)日：2012-01-24

申请号：US13026326

申请日：2011-02-14

申请人： Herbert Schäfer ,  Martin Franosch ,  Thomas Meister ,  Josef Böck

发明人： Herbert Schäfer ,  Martin Franosch ,  Thomas Meister ,  Josef Böck

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/02639 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02661

摘要： One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

摘要翻译： 本发明的一个实施例涉及利用原位差分外延在半导体主体上同时沉积多个不同结晶结构的方法。 在本发明的一个实施方案中，形成制备表面，得到两个不同的结晶区域，单晶硅衬底区域和隔离层区域。 单晶硅层和非晶硅层同时直接分布在单晶硅衬底区域和隔离层区域的制备表面上。 沉积包括形成两个或更多个子层。 可以为每个单独的子层改变工艺参数以优化沉积特性。

公开(公告)号：US20060191868A1

公开(公告)日：2006-08-31

申请号：US11346605

申请日：2006-02-02

申请人： Martin Franosch ,  Andreas Meckes ,  Klaus-Guenter Oppermann

发明人： Martin Franosch ,  Andreas Meckes ,  Klaus-Guenter Oppermann

IPC分类号： B44C1/22 ,  H01L21/302 ,  C23F1/00

CPC分类号： B81C1/00539 ,  B81B2203/0127

摘要： In the inventive method for the wet-chemical removal of a sacrificial material in a material structure, there is first provided the material structure, wherein the material structure has a treatment region with the sacrificial material accessible through an opening. Subsequently, the sacrificial material is brought into contact with a wet-chemical treatment agent through the opening for the removal of the sacrificial material, wherein a mechanical vibration is generated in the wet-chemical treatment agent or in the wet-chemical treatment agent and the material structure during the contacting of the sacrificial material with the wet-chemical treatment agent.

摘要翻译： 在用于在材料结构中湿化学去除牺牲材料的本发明的方法中，首先提供材料结构，其中材料结构具有处理区域，其中牺牲材料可通过开口接近。 随后，牺牲材料通过用于去除牺牲材料的开口与湿化学处理剂接触，其中在湿化学处理剂或湿化学处理剂中产生机械振动， 在牺牲材料与湿化学处理剂接触期间的材料结构。

公开(公告)号：US20050148205A1

公开(公告)日：2005-07-07

申请号：US10821798

申请日：2004-04-09

申请人： Martin Franosch ,  Andreas Meckes ,  Klaus-Gunter Oppermann

发明人： Martin Franosch ,  Andreas Meckes ,  Klaus-Gunter Oppermann

IPC分类号： H03H3/02 ,  H03H3/08 ,  H03H9/10 ,  H01L21/00

CPC分类号： B81C1/00333 ,  B81C2203/0136 ,  H03H3/02 ,  H03H3/08 ,  H03H9/105 ,  H03H9/1092 ,  Y10S156/93 ,  Y10S438/976 ,  Y10T29/49172 ,  Y10T29/49176 ,  Y10T29/4922 ,  Y10T29/49224 ,  Y10T29/49798 ,  Y10T156/1082 ,  Y10T156/11

摘要： In a method for producing a protective cover for a device formed in a substrate, at first a sacrificial structure is produced on the substrate, wherein the sacrificial structure comprises a first portion covering a first area of the substrate including the device and a second portion extending from the first portion into a second area of the substrate including no device. Then a first cover layer is deposited that encloses the sacrificial structure such that the second portion of the sacrificial structure is at least partially exposed. Then the sacrificial structure is removed, and the structure formed by the removal of the sacrificial structure is closed.

摘要翻译： 在用于生产用于形成在衬底中的器件的保护罩的方法中，首先在衬底上产生牺牲结构，其中牺牲结构包括覆盖包括该器件的衬底的第一区域的第一部分和延伸 从第一部分到不包括器件的衬底的第二区域。 然后沉积包围牺牲结构的第一覆盖层，使得牺牲结构的第二部分至少部分地暴露。 然后去除牺牲结构，并且通过去除牺牲结构形成的结构是封闭的。