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1.发明授权2-stage large bandwidth amplifier using diodes in the parallel feedback structure 有权2级大带宽放大器采用二极管并联反馈结构公开(公告)号：US06861908B2
公开(公告)日：2005-03-01
申请号：US10604478
申请日：2003-07-24
CPC分类号： H03F3/3432
摘要： There is disclosed an improved 2-stage large bandwidth amplifier (20) comprised of two stages formed by first and second bipolar transistors (Q1,Q2) configured in common emitter that are connected in series with their emitters connected to a first supply voltage (Gnd). The input signal (Vin) is applied to the base of said first transistor via an input terminal (11), while the output signal (Vout) is available at an output terminal (12) connected to the collector of said second transistor. A parallel feedback structure (13′) is provided. It consists, in a first branch, of two diodes (D1,D2) in series connected between a second supply voltage (Vcc) and the collector of the second bipolar transistor, and in another branch of a third bipolar transistor (Q3) configured in emitter follower with a resistor (Rf) in the emitter. The base and the collector of said third bipolar transistor are respectively connected to the common node of said diodes and to said second supply voltage. The resistor is connected to the common node of said first and second transistors to inject the feedback signal (Vf). Because, the two bodies have a low internal resistance and reduce the collector capacitance of the second transistor, the overall bandwidth of the improved amplifier is significantly extended in the very high frequencies (e.g. 20 GHz and above).
摘要翻译： 公开了一种改进的2级大带宽放大器（20），包括由配置在共发射极中的第一和第二双极晶体管（Q1，Q2）形成的两级，它们与连接到第一电源电压（Gnd ）。 输入信号（Vin）经由输入端子（11）施加到所述第一晶体管的基极，而输出信号（Vout）在连接到所述第二晶体管的集电极的输出端子（12）处可用。 提供并行反馈结构（13'）。 它包括在第一分支中串联连接在第二电源电压（Vcc）和第二双极晶体管的集电极之间的两个二极管（D1，D2），以及在第三分支中配置的第三双极晶体管 射极跟随器在发射极中具有电阻（Rf）。 所述第三双极晶体管的基极和集电极分别连接到所述二极管的公共节点和所述第二电源电压。 电阻器连接到所述第一和第二晶体管的公共节点以注入反馈信号（Vf）。 因为这两个机体具有较低的内部电阻并且降低了第二晶体管的集电极电容，所以改进的放大器的总带宽在非常高的频率（例如20GHz及以上）中被显着地扩展。
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公开(公告)号：US06914479B1
公开(公告)日：2005-07-05
申请号：US10604479
申请日：2003-07-24
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F3/45278 , H03F3/45973 , H03F2203/45521 , H03F2203/45652
摘要： There is disclosed an improved differential amplifier (20) having a feedback loop that generates an amplified output signal (Vout) from an input signal (Vin) supplied by a preceding stage. It comprises an input matching circuit (11) connected to said preceding stage, a buffer (22) and an amplification section (12) connected in series in the direct amplification line, a first amplifier (16), a RC network (17′) and a second amplifier (23) connected in series in a parallel loop between the outputs and the inputs of the amplification section that generate the feedback signal. The role of said buffer and second amplifier associated in a dedicated direct and feedback signal combining block (21) is to respectively isolate the input signal and the feedback signal from the summing nodes (A′,B′) at the amplification section inputs. As a result, the summation of the input signal and the feedback signal is improved, the DC component of the output signal is filtered out in order to significantly reduce the DC offset. In addition, the input impedance matching represented by parameter S11 is considerably improved.
摘要翻译： 公开了一种具有反馈回路的改进的差分放大器（20），该反馈回路从由前一级提供的输入信号（Vin）产生放大的输出信号（Vout）。 它包括连接到所述前级的输入匹配电路（11），串联连接在直接放大线路中的缓冲器（22）和放大部分（12），第一放大器（16），RC网络（17'） 以及在产生反馈信号的输出与放大部分的输入之间并联连接的第二放大器（23）。 在专用直接和反馈信号组合块（21）中相关联的所述缓冲器和第二放大器的作用是在放大部分输入端分别隔离来自求和节点（A'，B'）的输入信号和反馈信号。 结果，改善了输入信号和反馈信号的总和，输出信号的直流分量被滤除，以便显着减小直流偏移。 此外，由参数S 11表示的输入阻抗匹配得到显着改善。
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公开(公告)号：US07944280B2
公开(公告)日：2011-05-17
申请号：US12198183
申请日：2008-08-26
CPC分类号： G05F3/30
摘要： A circuit for providing a bandgap voltage. The circuit includes a classic bandgap reference voltage generation circuit including first end second serially connected transistors acting as a current mirror to another portion of the classical bandgap reference circuit and being coupled between a supply voltage Vdd and an output resistor. The circuit also includes a current trimming circuit coupled in parallel with the classical bandgap reference generation circuit including a fixed element portion including a plurality of transistors and a switch portion including a plurality of switches. Each of the plurality of transistors is coupled to the supply voltage Vdd and to a one of the plurality of switches and each switch includes a fuse.
摘要翻译： 用于提供带隙电压的电路。 该电路包括经典的带隙参考电压产生电路，其包括用作经典带隙基准电路的另一部分的电流镜的第一端第二串联连接的晶体管，并耦合在电源电压Vdd和输出电阻之间。 电路还包括与经典带隙基准产生电路并联耦合的电流微调电路，其包括包括多个晶体管的固定元件部分和包括多个开关的开关部分。 多个晶体管中的每一个耦合到电源电压Vdd和多个开关中的一个，每个开关包括熔丝。
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公开(公告)号：US20090289697A1
公开(公告)日：2009-11-26
申请号：US12198183
申请日：2008-08-26
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： A circuit for providing a bandgap voltage. The circuit includes a classic bandgap reference voltage generation circuit including first end second serially connected transistors acting as a current mirror to another portion of the classical bandgap reference circuit and being coupled between a supply voltage Vdd and an output resistor. The circuit also includes a current trimming circuit coupled in parallel with the classical bandgap reference generation circuit including a fixed element portion including a plurality of transistors and a switch portion including a plurality of switches. Each of the plurality of transistors is coupled to the supply voltage Vdd and to a one of the plurality of switches and each switch includes a fuse.
摘要翻译： 用于提供带隙电压的电路。 该电路包括经典的带隙参考电压产生电路，其包括用作电流镜的第一端第二串联连接的晶体管，并经耦合在电源电压Vdd和输出电阻之间。 电路还包括与经典带隙基准产生电路并联耦合的电流微调电路，其包括包括多个晶体管的固定元件部分和包括多个开关的开关部分。 多个晶体管中的每一个耦合到电源电压Vdd和多个开关中的一个，每个开关包括熔丝。
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5.发明授权Circuit for testing a semiconductor chip having embedded arrays intermixed with logic 失效用于测试具有与逻辑混合的嵌入式阵列的半导体芯片的电路
公开(公告)号：US5717696A
公开(公告)日：1998-02-10
申请号：US391997
申请日：1995-02-21
申请人： Bertrand Gabillard , Michel Rivier
发明人： Bertrand Gabillard , Michel Rivier
IPC分类号： G01R31/28 , G01R31/30 , G11C29/00 , G11C29/02 , G11C29/50 , G11C29/56 , H01L21/66 , H05K10/00
CPC分类号： G11C29/50 , G01R31/3004
摘要： A test circuit applicable to chips having embedded arrays intermixed with logic is described. Depending on a control signal, the test circuit connects or isolates the arrays to and from the logic. The test circuit operates as a switch placed between the power supply rail of the logic and the power supply rail of the arrays. All input gates are cross-connected to the power supply rail of the logic, and each output gate is connected to the corresponding power supply rail of the arrays. During TEST mode, the control signal turns off the test circuit, cutting off the arrays. The logic is tested while the memory cells remain unselected. Faulty chips are rejected. When the value of the control signal is inverted, a control gate connects all the power supply rails of the arrays to the power supply rail of the logic. The test sequence for the embedded array is then applied. Faulty memory cells are replaced with repairable ones; otherwise, the faulty chips are rejected. Thus, the manufacturing yield of the mixed chips is improved.
摘要翻译： 描述了适用于具有与逻辑混合的嵌入式阵列的芯片的测试电路。 根据控制信号，测试电路将阵列与逻辑电路连接或隔离。 测试电路用作逻辑电源轨和阵列的电源轨之间的开关。 所有输入门都与逻辑电源轨交叉连接，每个输出门连接到阵列的相应电源轨。 在TEST模式下，控制信号关闭测试电路，切断阵列。 当存储器单元保持未选择时，该逻辑被测试。 错误的芯片被拒绝。 当控制信号的值反转时，控制栅将阵列的所有电源轨连接到逻辑电源轨。 然后应用嵌入式阵列的测试序列。 故障记忆单元被可修复的单元替换; 否则，故障芯片被拒绝。 因此，混合芯片的制造成品率提高。
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公开(公告)号：US5267216A
公开(公告)日：1993-11-30
申请号：US920086
申请日：1992-07-27
CPC分类号： G11C8/18
摘要： A plurality of local address transition detector (LATD) circuits, one per address bit signal (Ai), of the type used in SRAMs to generate an on-chip clock pulse (LATDSi) that insures a correct timing of internal circuits such as sense amplifiers and address decoders that are essential for a correct READ/WRITE operation of the SRAM. According to one aspect of the invention, each LATD circuit includes: a first bipolar transistor (T1) serially connected with a first FET device (N1) forming a first branch; a second bipolar transistor (T2) serially connected with a second FET device (N2) forming a second branch. The first and second branches are connected in parallel between a first supply voltage (Vcc) and a common output node (N) connected to a circuit output terminal (30-i) where the output signal (LATDSi) generated by the LATD circuit (22-i) is available. The first and second bipolar transistors (T1, T2) are respectively driven by the address signal (Ai') and its complement (Ai') at the ECL voltage levels and the second and first FET devices are respectively driven by the address signal (Ai*' ) and its complement (Ai*') at the CMOS voltage levels. As a result of this design of the LATD circuit, the delays in critical paths in BICMOS circuits incorporating the LATD circuit may be significantly reduced relative to BICMOS circuits utilizing conventional LATD circuits.
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7.发明授权
公开(公告)号：US5627963A
公开(公告)日：1997-05-06
申请号：US466563
申请日：1995-06-06
IPC分类号： G06F12/0864 , G06F12/0895 , G11C11/413 , G11C29/00 , G11C29/04 , G06F11/00
CPC分类号： G11C29/80 , G06F12/0864 , G06F12/0895 , G11C29/846
摘要： A cache memory architecture having a separate redundant read bus fully dedicated to redundancy and fed by a single spare sub-array common to all memory sub-arrays of the cache memory. Redundant sense amplifiers are dotted to the redundant read bus, and normal sense amplifiers are connected to a main read bus. Normal and redundant data are valid and available at the same time at the outputs of the normal and redundant sense amplifiers. When the late select address signals become valid, then the correct information can be selected via a multiplexer provided with an INHIBIT input. The multiplexer is normally controlled by decoded signals generated by a decoder, unless redundancy is required. If redundancy is required, the information generated by the bit address comparator forces the multiplexer, via the INHIBIT input, to select the redundant read bus, instead of one read bus of the main read bus, and to output the redundant byte as the selected one.
摘要翻译： 高速缓存存储器架构具有完全专用于冗余的单独的冗余读出总线，并由缓存存储器的所有存储器子阵列共同的单个备用子阵列馈送。 冗余读出放大器点到冗余读总线，而正常读出放大器连接到主读总线。 正常和冗余数据在正常和冗余读出放大器的输出端同时有效并可用。 当后期选择地址信号变为有效时，可以通过一个提供INHIBIT输入的复用器来选择正确的信息。 多路复用器通常由解码器生成的解码信号控制，除非需要冗余。 如果需要冗余，位地址比较器产生的信息将通过INHIBIT输入来强制多路复用器选择冗余读总线，而不是主读总线的一个读总线，并输出冗余字节作为选定的一个 。
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8.发明授权Level-shifter circuit for high-speed low-power BiCMOS ECL to CMOS input buffers 失效用于高速低功率BICMOS ECL到CMOS输入缓冲器的电平更换电路
公开(公告)号：US5173624A
公开(公告)日：1992-12-22
申请号：US788956
申请日：1991-11-07
IPC分类号： H03K3/356 , H03K19/00 , H03K19/0175 , H03K19/0185 , H03K19/0944
CPC分类号： H03K19/0016 , H03K19/0013 , H03K19/017527 , H03K19/09448 , H03K3/356113
摘要： Input ECL level signals are received and converted into output CMOS level signals by input buffer (30). The input buffer (30) biased between first and second supply voltage (Vcc, Vee) and is comprised of three stages. The first stage (11A) consists of a conventional emitter-follower transistor (Q1) and a current-switch (13) connected in series. The input signal VIN at the ECL level is applied to the base of the emitter-follower transistor (Q1). The output signals (VA, VB) obtained therefrom drive a second stage which consists of an input buffer circuit (20), which supplies two pairs of output signals (V1) V2; V1', V2') for each phase. Each pair of output signals drives an output driver (31; 31') forming the third stage. The input buffer circuit (20) is composed of two NPN bipolar transistor (T1; T2) connected in an emitter-follower configuration forming two branches. In each branch, the emitter load consists of three FET devices: two PFETs (P1, P3; P2, P4 ) and one NFET (N1; N2) serially connected. The common node (E; F) between the PFETs in one branch, is cross-coupled to the gate electrode of the NFET (N2; N1) of the other branch. The gate electrode of the PFET (P1; P2) connected to the emitter of the bipolar transistor (T1; T2) in one branch is driven by the potential of the common node formed by the other PFET (P4, P3) and the NFET (N2; N1) in the other branch. The IN PHASE (VOUT) and OUT OF PHASE (VOUT) circuit output signals are available at the circuit output terminals (32; 32') of said output drivers (31; 31') at the CMOS levels.
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公开(公告)号：US4644189A
公开(公告)日：1987-02-17
申请号：US649453
申请日：1984-09-11
申请人： Bertrand Gabillard
发明人： Bertrand Gabillard
IPC分类号： G11C11/413 , G11C11/418 , H01L27/10 , H03K19/094 , G11C8/00 , H03K19/017
CPC分类号： G11C11/418
摘要： A decoder circuit for a static random access memory cell and which may be integrated in monolithic form using gallium arsenide field effect transistors. The circuit comprises a first logic NOR-gate P.sub.1 having (n+1) inputs on which the n coded memory address signals or their complements are received, and also the chip-enable selection signal SB. The gate P.sub.1 is connected by a load resistor R to a supply voltage V.sub.DD1. A second NOR-gate P.sub.2 receives the same inputs as the gate P.sub.1 and has as its load a transistor T.sub.0 the gate electrode of which receives the output of the gate P.sub.1 and the drain of which is connected to a power supply voltage V.sub.DD2 which is less than V.sub.DD1. The voltage V.sub.DD2 is also the supply voltage for the memory cell, and is set at the clipping value of the gate junctions of the constituent transistors of that cell. The output V.sub.S of the decoder is produced at the drains of the transistors forming the second NOR-gate P.sub.2 which are connected to the source electrode of the load transistor T.sub.0. The inputs of the NOR-gates receive a chip-enable selection signal SB after application of the n coded memory address signals, thereby achieving reduced access time for the memory cell.
摘要翻译： 一种用于静态随机存取存储器单元的解码器电路，其可以使用砷化镓场效应晶体管集成在单片形式中。 电路包括具有（n + 1）个输入的第一逻辑NOR门P1，其上接收了n个编码存储器地址信号或其补码，以及芯片使能选择信号SB。 门P1通过负载电阻R连接到电源电压VDD1。 第二NOR门P2接收与栅极P1相同的输入，并且具有作为其负载的晶体管T0，其栅电极接收栅极P1的输出，其漏极连接到较小的电源电压VDD2 比VDD1。 电压VDD2也是存储单元的电源电压，并且被设置在该单元的构成晶体管的栅极结的削波值。 解码器的输出VS在形成与负载晶体管T0的源极连接的第二NOR-门P2的晶体管的漏极处产生。 NOR门的输入在施加n个编码存储器地址信号之后接收芯片使能选择信号SB，从而实现存储单元的访问时间减少。
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10.发明授权Receiver having full signal path differential offset cancellation capabilities 失效接收机具有全信号路径差分偏移消除功能公开(公告)号：US07180354B2
公开(公告)日：2007-02-20
申请号：US10906988
申请日：2005-03-15
IPC分类号： H03L5/00
CPC分类号： H03F3/45775 , G11C27/026
摘要： There is described an improved receiver which first comprises an analog input amplifier a sample and hold differential circuit and two stages of differential comparators that are connected in series, wherein the first stage consists of two comparators and the second stage of one comparator. By properly activating the switches with signals generated by a dedicated control logic, the input differential signal is sampled in the sample and hold circuit to generate first and second differential signals. The first differential signal holds a first state and the second differential signal propagates the second state. As result, the signal output by the second comparator stage reflects the differential offset minus the offset compensation.
摘要翻译： 描述了一种改进的接收机，其首先包括模拟输入放大器，采样保持差分电路和串联连接的两级差分比较器，其中第一级由两个比较器和一个比较器的第二级组成。 通过用专用控制逻辑产生的信号正确激活开关，输入差分信号在取样和保持电路中被采样，以产生第一和第二差分信号。 第一差分信号保持第一状态，第二差分信号传播第二状态。 结果，由第二比较器级输出的信号反映差分偏移减去偏移补偿。
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