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    Process for fabricating a semiconductor device using a silicon-rich silicon nitride ARC
    1.
    发明授权
    Process for fabricating a semiconductor device using a silicon-rich silicon nitride ARC 有权
    使用富硅氮化物ARC制造半导体器件的工艺

    公开(公告)号：US06395644B1

    公开(公告)日：2002-05-28

    申请号：US09484606

    申请日：2000-01-18

    申请人： Dawn M. Hopper ,  Minh Van Ngo ,  David K. Foote

    发明人： Dawn M. Hopper ,  Minh Van Ngo ,  David K. Foote

    IPC分类号： H01L21302

    CPC分类号： H01L21/3185 ,  H01L21/32139 ,  Y10S438/952

    摘要： A process for fabricating a semiconductor device using an ARC layer includes the formation of a silicon-rich silicon nitride material to provide an anti-reflective layer over a electrically conductive or semiconductor surface. The silicon-rich silicon nitride material is plasma deposited to provide a material having a desired refractive index, thickness uniformity, and density. The process includes the formation of a device layer on a semiconductor substrate. The device layer includes at least a silicon layer and a silicon oxide layer. A silicon-rich silicon nitride layer is formed to overlie the device layer. The silicon-rich silicon nitride material can be selectively etched, such that the silicon material and the silicon oxide material in the underlying device layer are not substantially etched.

    摘要翻译： 使用ARC层制造半导体器件的方法包括形成富硅的氮化硅材料，以在导电或半导体表面上提供抗反射层。 富硅氮化硅材料被等离子体沉积以提供具有期望的折射率，厚度均匀性和密度的材料。 该方法包括在半导体衬底上形成器件层。 器件层至少包括硅层和氧化硅层。 形成富含硅的氮化硅层以覆盖器件层。 可以选择性地蚀刻富硅的氮化硅材料，使得底层器件层中的硅材料和氧化硅材料基本上不被蚀刻。

    Deposition control of stop layer and dielectric layer for use in the formation of local interconnects
    2.
    发明授权
    Deposition control of stop layer and dielectric layer for use in the formation of local interconnects 失效
    用于形成局部互连的停止层和介电层的沉积控制

    公开(公告)号：US6060393A

    公开(公告)日：2000-05-09

    申请号：US993888

    申请日：1997-12-18

    申请人： Minh Van Ngo ,  Darin A. Chan ,  David K. Foote

    发明人： Minh Van Ngo ,  Darin A. Chan ,  David K. Foote

    IPC分类号： H01L21/768 ,  H01L21/304

    CPC分类号： H01L21/76895 ,  H01L21/76801

    摘要： A deposition method allows for the forming of a uniform dielectric stop layer that is substantially void of defects caused by outgassing effects. The stop layer is deposited in a reactor chamber at a higher than normal temperature of at least 480.degree. C. The stop layer is then combined with an overlying dielectric layer to provide an inter-level dielectric structure through which a local interconnect can be formed to provide a conductive path to one or more regions of the underlying semiconductor devices.

    摘要翻译： 沉积方法允许形成基本上没有由除气效应引起的缺陷的均匀的电介质停止层。 停止层沉积在高于至少480℃的常温的反应器室中。然后将停止层与覆盖的介电层组合以提供层间电介质结构，通过该层间电介质结构可以形成局部互连 为下面的半导体器件的一个或多个区域提供导电路径。

    Process for forming bottom anti-reflection coating for semiconductor fabrication photolithography which inhibits photoresist footing
    3.
    发明授权
    Process for forming bottom anti-reflection coating for semiconductor fabrication photolithography which inhibits photoresist footing 失效
    用于形成抑制光致抗蚀剂底物的用于半导体制造光刻的底部抗反射涂层的方法

    公开(公告)号：US06903007B1

    公开(公告)日：2005-06-07

    申请号：US08857055

    申请日：1997-05-15

    申请人： David K. Foote ,  Minh Van Ngo

    发明人： David K. Foote ,  Minh Van Ngo

    IPC分类号： H01L21/027 ,  H01L21/312 ,  H01L21/314 ,  H01L21/768 ,  H01L23/522 ,  H01L21/4763

    CPC分类号： H01L21/02126 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/0276 ,  H01L21/3121 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/76802 ,  H01L21/76895 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An anti-reflective coating is formed between a material layer which is to be patterned on a semiconductor structure using photolithography, and an overlying photoresist layer. The anti-reflective coating suppresses reflections from the material layer surface into the photoresist layer that could degrade the patterning. The anti-reflective coating includes an anti-reflective layer of silicon oxime, silicon oxynitride, or silicon nitride, and a barrier layer which is grown on the anti-reflective layer using a nitrous oxide plasma discharge to convert a surface portion of the anti-reflective layer into silicon dioxide. The barrier layer prevents interaction between the anti-reflective layer and the photoresist layer that could create footing. The anti-reflective layer is deposited on the material layer using Plasma Enhanced Chemical Vapor Deposition (PECVD) in a reactor. The barrier layer is grown on the anti-reflective layer in-situ in the same reactor, thereby maximizing throughput.

    摘要翻译： 在使用光刻法在半导体结构上图案化的材料层和上覆的光致抗蚀剂层之间形成抗反射涂层。 抗反射涂层抑制从材料层表面到可能降解图案化的光致抗蚀剂层的反射。 抗反射涂层包括硅肟，氮氧化硅或氮化硅的抗反射层，以及阻挡层，其使用一氧化二氮等离子体放电在抗反射层上生长以将抗反射层转化成抗反射层， 反射层成二氧化硅。 阻挡层防止可产生基底的抗反射层和光致抗蚀剂层之间的相互作用。 在反应器中使用等离子体增强化学气相沉积（PECVD）将抗反射层沉积在材料层上。 阻挡层在同一反应器中原位生长在抗反射层上，从而最大化生产量。

    Methods for making a semiconductor device with improved hot carrier lifetime
    7.
    发明授权
    Methods for making a semiconductor device with improved hot carrier lifetime 失效
    制造具有改善的热载流子寿命的半导体器件的方法

    公开(公告)号：US6022799A

    公开(公告)日：2000-02-08

    申请号：US993828

    申请日：1997-12-18

    申请人： David K. Foote ,  Minh Van Ngo ,  Darin A. Chan

    发明人： David K. Foote ,  Minh Van Ngo ,  Darin A. Chan

    IPC分类号： H01L21/027 ,  H01L21/312 ,  H01L21/314 ,  H01L21/768 ,  H01L21/8247

    CPC分类号： H01L21/76895 ,  H01L21/0276 ,  H01L21/3121 ,  H01L21/3145

    摘要： A local interconnection to a device region in/on a substrate is formed by depositing either silicon oxynitride or silicon oxime as an etch stop layer, at a temperature of less than about 480.degree. C. to increase the hot carrier injection (HCI) lifetime of the resulting semiconductor device. A dielectric layer is then deposited over the etch stop layer and through-holes are etched exposing the etch stop layer using a first etching process. A second etching process is then conducted, which etches through the etch stop layer exposing at least one device region. The resulting through-hole is then filled with conductive material(s) to form a local interconnection.

    摘要翻译： 通过在小于约480℃的温度下沉积硅氧氮化物或硅肟作为蚀刻停止层来形成与衬底中/之上的器件区域的局部互连，以增加热载流子注入（HCI）寿命 得到的半导体器件。 然后将介电层沉积在蚀刻停止层上，并且使用第一蚀刻工艺蚀刻暴露蚀刻停止层的通孔。 然后进行第二蚀刻工艺，其蚀刻通过蚀刻停止层暴露至少一个器件区域。 然后将所形成的通孔用导电材料填充以形成局部互连。

    Methods and arrangements for insulating local interconnects for improved alignment tolerance and size reduction
    9.
    发明授权
    Methods and arrangements for insulating local interconnects for improved alignment tolerance and size reduction 有权
    用于绝缘局部互连的方法和布置，以改善对准公差和减小尺寸

    公开(公告)号：US06399480B1

    公开(公告)日：2002-06-04

    申请号：US09515319

    申请日：2000-02-29

    申请人： William G. En ,  Darin A. Chan ,  David K. Foote ,  Fei Wang ,  Minh Van Ngo

    发明人： William G. En ,  Darin A. Chan ,  David K. Foote ,  Fei Wang ,  Minh Van Ngo

    IPC分类号： H01L714263

    CPC分类号： H01L21/76895 ,  H01L21/76897

    摘要： At least one patterned dielectric layer is provided within a transistor arrangement to prevent a local interconnect from electrically contacting,the gate conductor due to misalignments during the damascene formation of etched openings used in forming local interconnects. By selectively etching through a plurality of dielectric layers during the local interconnect etching process, the patterned dielectric layer is left in place to prevent short-circuiting of the gate to an adjacent local interconnect that is slightly misaligned.

    摘要翻译： 在晶体管布置内提供至少一个图案化的介电层，以防止局部互连在形成局部互连的蚀刻开口的镶嵌层形成期间由于不对准导致栅极导体电接触。 通过在局部互连蚀刻工艺期间通过选择性蚀刻穿过多个电介质层，将图案化的介电层留在原位以防止栅极短路到相邻的局部互连，其稍微错位。

    Local interconnects for improved alignment tolerance and size reduction
    10.
    发明授权
    Local interconnects for improved alignment tolerance and size reduction 失效
    局部互连，用于改善对准公差和减小尺寸

    公开(公告)号：US6121663A

    公开(公告)日：2000-09-19

    申请号：US992952

    申请日：1997-12-18

    申请人： William G. En ,  Darin A. Chan ,  David K. Foote ,  Fei Wang ,  Minh Van Ngo

    发明人： William G. En ,  Darin A. Chan ,  David K. Foote ,  Fei Wang ,  Minh Van Ngo

    IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    CPC分类号： H01L21/76895 ,  H01L21/76897

    摘要： At least one patterned dielectric layer is provided within a transistor arrangement to prevent a local interconnect from electrically contacting the gate conductor due to misalignments during the damascene formation of etched openings used in forming local interconnects. By selectively etching through a plurality of dielectric layers during the local interconnect etching process, the patterned dielectric layer is left in place to prevent short-circuiting of the gate to an adjacent local interconnect that is slightly misaligned.

    摘要翻译： 在晶体管布置内提供至少一个图形化的介电层，以防止局部互连在形成局部互连所用的蚀刻开口的镶嵌层形成期间由于不对准而电接触栅极导体。 通过在局部互连蚀刻工艺期间通过选择性蚀刻穿过多个电介质层，将图案化的介电层留在原位以防止栅极短路到相邻的局部互连，其稍微错位。