公开(公告)号：US06265294B1

公开(公告)日：2001-07-24

申请号：US09373084

申请日：1999-08-12

申请人： Stephen Keetai Park ,  Guarionex Morales ,  Bharath Rangarajan ,  Jeff Shields

发明人： Stephen Keetai Park ,  Guarionex Morales ,  Bharath Rangarajan ,  Jeff Shields

IPC分类号： H01L21425

CPC分类号： H01L23/5329 ,  H01L21/0276 ,  H01L21/31144 ,  H01L21/3144 ,  H01L21/76829 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fabrication method reduces the amount of discoloration on interlevel dielectric layers due to anti-reflective coatings (ARC). The invention utilizes a barrier layer, such as, silicon nitride (SiN) that prevents the anti-reflective coating from contacting the interlevel dielectric layer (ILD0). The anti-reflective coating can be silicon oxynitride (SiON) deposited by LPCVD or PECVD.

摘要翻译： 制造方法减少了由于抗反射涂层（ARC）引起的层间电介质层上的变色量。 本发明利用阻挡层，例如防止抗反射涂层与层间介质层（ILD0）接触的氮化硅（SiN）。 抗反射涂层可以是通过LPCVD或PECVD沉积的氮氧化硅（SiON）。

公开(公告)号：US06420104B1

公开(公告)日：2002-07-16

申请号：US09705941

申请日：2000-11-03

申请人： Bharath Rangarajan ,  Stephen Keetai Park ,  Guarionex Morales

发明人： Bharath Rangarajan ,  Stephen Keetai Park ,  Guarionex Morales

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/76816 ,  H01L21/76832

摘要： A method of reducing contact size in an integrated circuit includes providing an insulating layer over a semiconductor substrate including a plurality of gate structures, creating an aperture extending through the insulating layer and having side walls, providing a spacer on the side walls of the aperture, and providing a contact in the aperture. The lateral sides of the contact abut the spacer. A contact structure is also disclosed in which a spacer separates a contact from a gate structure to avoid charge gain or loss between the contact and gate structure.

摘要翻译： 减小集成电路中的接触尺寸的方法包括在包括多个栅极结构的半导体衬底之上提供绝缘层，形成延伸穿过绝缘层并具有侧壁的孔，在孔的侧壁上提供间隔物， 并在孔中提供接触。 接触件的侧面靠垫片。 还公开了一种接触结构，其中隔离物将接触与栅极结构分离以避免接触和栅极结构之间的电荷增益或损耗。

公开(公告)号：US06265273B1

公开(公告)日：2001-07-24

申请号：US09359502

申请日：1999-07-23

申请人： Steven C. Avanzino ,  Stephen Keetai Park ,  Bharath Rangarajan ,  Jeffrey A. Shields ,  Larry Yu Wang ,  Guarionex Morales

发明人： Steven C. Avanzino ,  Stephen Keetai Park ,  Bharath Rangarajan ,  Jeffrey A. Shields ,  Larry Yu Wang ,  Guarionex Morales

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/31116

摘要： A method of forming spacers in an integrated circuit is disclosed herein. The method includes providing a gate structure over a semiconductor substrate, depositing a spacer material adjacent lateral sides of the gate structure, and etching the spacer material to form spacers. The spacers have minimal surface area exposed to direct sputter.

摘要翻译： 本文公开了一种在集成电路中形成间隔物的方法。 该方法包括在半导体衬底上提供栅极结构，在栅极结构的侧面附近沉积间隔物材料，并蚀刻间隔物材料以形成间隔物。 间隔物具有暴露于直接溅射的最小表面积。

公开(公告)号：US06287917B1

公开(公告)日：2001-09-11

申请号：US09392675

申请日：1999-09-08

申请人： Stephen Keetai Park ,  Tim Thurgate ,  Bharath Rangarajan

发明人： Stephen Keetai Park ,  Tim Thurgate ,  Bharath Rangarajan

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A process for fabricating an MNOS device includes the steps of forming a hardmask containing at least first and second openings over a core array area of a semiconductor substrate. An angle doping process is carried out to form halo regions in precise locations within the substrate at the edges of the first and second openings in the hardmask. Another doping process is carried out to form buried bit-lines in the substrate using the hardmask as a doping mask. Once the halo regions and the buried bit-lines are formed, the hardmask is removed and a composite dielectric layer is formed overlying the substrate. A gate layer is deposited to overlie the composite dielectric layer, and an etching process is carried out to form a control gate electrode and a charge storage electrode in the MNOS device

摘要翻译： 制造MNOS器件的方法包括以下步骤：在半导体衬底的芯阵列区域上形成至少包含第一和第二开口的硬掩模。 进行角度掺杂处理以在硬掩模中的第一和第二开口的边缘处在衬底内的精确位置中形成晕圈。 进行另一种掺杂工艺以使用硬掩模作为掺杂掩模在衬底中形成掩埋位线。 一旦形成了光晕区域和掩埋位线，就去除了硬掩模，并且在衬底上形成复合介电层。 沉积栅极层以覆盖复合介电层，并且进行蚀刻处理以在MNOS器件中形成控制栅电极和电荷存储电极

公开(公告)号：US06306758B1

公开(公告)日：2001-10-23

申请号：US09567534

申请日：2000-05-10

申请人： Stephen Keetai Park

发明人： Stephen Keetai Park

IPC分类号： H01L214763

CPC分类号： H01L21/28061 ,  H01L21/28123 ,  H01L21/28273

摘要： A graded cap layer that reduces the overall height of a layer stack and provides for increased process control during subsequent patterning of the layer stack, is described with a method of making the same. The graded cap layer is configured to function as a cap layer to prevent an underlying silicide layer from lifting, a barrier layer to prevent the underlying silicide layer from being oxidized during subsequent processes, a stop layer to prevent over-etching during subsequent self-aligned source (SAS) patterning processes, and/or an anti-reflective coating (ARC) to improve the resolution of subsequent patterning processes. The graded cap layer is a relatively thin layer of silicon oxynitride with varying concentrations of nitrogen. The cap layer is deposited in a single chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) chamber.

摘要翻译： 通过制造相同的方法来描述降低层堆叠的总体高度并且在随后的层叠图案化期间提供增加的工艺控制的分级盖层。 渐变盖层被配置为用作覆盖层以防止下面的硅化物层提升，阻挡层以防止下一个硅化物层在后续工艺期间被氧化，阻止层以防止随后自对准期间的过度蚀刻 源（SAS）图案化工艺和/或抗反射涂层（ARC））以提高随后的图案化工艺的分辨率。 分级覆盖层是具有不同浓度的氮的相对薄的氮氧化硅层。 盖层沉积在单一化学气相沉积（CVD）或等离子体增强化学气相沉积（PECVD）室中。

公开(公告)号：US6100559A

公开(公告)日：2000-08-08

申请号：US134525

申请日：1998-08-14

申请人： Stephen Keetai Park

发明人： Stephen Keetai Park

IPC分类号： H01L21/28 ,  H01L21/331 ,  H01L21/8222

CPC分类号： H01L21/28061 ,  H01L21/28123 ,  H01L21/28273

摘要： A graded cap layer that reduces the overall height of a layer stack and provides for increased process control during subsequent patterning of the layer stack, is described with a method of making the same. The graded cap layer is configured to function as a cap layer to prevent an underlying silicide layer from lifting, a barrier layer to prevent the underlying silicide layer from being oxidized during subsequent processes, a stop layer to prevent over-etching during subsequent self-aligned source (SAS) patterning processes, and/or an anti-reflective coating (ARC) to improve the resolution of subsequent patterning processes. The graded cap layer is a relatively thin layer of silicon oxynitride with varying concentrations of nitrogen. The cap layer is deposited in a single chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) chamber.

摘要翻译： 通过制造相同的方法来描述降低层堆叠的总体高度并且在随后的层叠图案化期间提供增加的工艺控制的分级盖层。 渐变盖层被配置为用作覆盖层以防止下面的硅化物层提升，阻挡层以防止下一个硅化物层在后续工艺期间被氧化，阻止层以防止随后自对准期间的过度蚀刻 源（SAS）图案化工艺和/或抗反射涂层（ARC））以提高随后的图案化工艺的分辨率。 分级覆盖层是具有不同浓度的氮的相对薄的氮氧化硅层。 盖层沉积在单一化学气相沉积（CVD）或等离子体增强化学气相沉积（PECVD）室中。

公开(公告)号：US06232635B1

公开(公告)日：2001-05-15

申请号：US09543991

申请日：2000-04-06

申请人： Larry Yu Wang ,  Steven C. Avanzino ,  Jeffrey A. Shields ,  Stephen Keetai Park

发明人： Larry Yu Wang ,  Steven C. Avanzino ,  Jeffrey A. Shields ,  Stephen Keetai Park

IPC分类号： H01L291788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： An article and method of manufacturing a semiconductor flash cell. The method includes producing an isolation formation layer on a silicon substrate, forming an oxide on the isolation formation layer, growing a tunnel oxide layer thereon, depositing a first poly silicon layer, masking and etching the first poly silicon layer, depositing a second poly silicon layer and performing a blanket etch back step, forming an oxide/nitride/oxide layer forming a third poly-silicon layer and depositing a silicide layer thereon.

摘要翻译： 制造半导体闪存单元的制品和方法。 该方法包括在硅衬底上制造隔离层，在隔离层上形成氧化物，在其上生长隧道氧化物层，沉积第一多晶硅层，掩蔽和蚀刻第一多晶硅层，沉积第二多晶硅 层并进行覆盖层回蚀步骤，形成形成第三多晶硅层的氧化物/氮化物/氧化物层并在其上沉积硅化物层。

公开(公告)号：US06486506B1

公开(公告)日：2002-11-26

申请号：US09532293

申请日：2000-03-23

申请人： Stephen Keetai Park ,  Jeffrey A. Shields

发明人： Stephen Keetai Park ,  Jeffrey A. Shields

IPC分类号： H01L2972

CPC分类号： H01L27/11521 ,  H01L23/3192 ,  H01L23/564 ,  H01L27/115 ,  H01L29/42324 ,  H01L2924/0002 ,  H01L2924/3025 ,  H01L2924/00

摘要： An integrated circuit is designed to reduce charge gain and charge loss in a flash memory or flash programmable read-only memory. Charge gain and loss caused by moisture or hydrogen diffusion or alternately small contact-to-floating gate distance is reduced by a capping layer disposed over a gate stack and a base layer of the flash memory. The capping layer includes a buffer layer, a first insulative layer, and a second insulative layer. The etch characteristics of at least the first and second insulative layer differs from an interlevel dielectric to control the dimensions of a contact extending through the interlevel dielectric and the capping layer to the base layer.

摘要翻译： 集成电路设计用于减少闪存或闪存可编程只读存储器中的充电增益和电荷损耗。 通过设置在闪存的栅极堆叠和基极层上的覆盖层减少由水分或氢扩散引起的电荷增益和损耗，或者交替地小的接触到浮置栅极距离。 封盖层包括缓冲层，第一绝缘层和第二绝缘层。 至少第一绝缘层和第二绝缘层的蚀刻特性不同于层间电介质，以控制延伸穿过层间电介质和覆盖层到基底层的接触层的尺寸。

公开(公告)号：US06355555B1

公开(公告)日：2002-03-12

申请号：US09493384

申请日：2000-01-28

申请人： Stephen Keetai Park

发明人： Stephen Keetai Park

IPC分类号： H01L214763

CPC分类号： H01L21/7681 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/7688 ,  H01L21/76885

摘要： A method is provided for forming a copper interconnect, the method including forming a sacrificial dielectric layer above a structure layer, forming an opening in the sacrificial dielectric layer and forming a copper layer above the sacrificial dielectric layer and in the opening. The method also includes forming the copper interconnect by removing portions of the copper layer above the sacrificial dielectric layer, leaving the copper interconnect in the opening. The method further includes removing the sacrificial dielectric layer above the structure and adjacent the copper interconnect, and forming a low dielectric constant dielectric layer above the structure and adjacent the copper interconnect.

摘要翻译： 提供一种用于形成铜互连的方法，该方法包括在结构层上形成牺牲电介质层，在牺牲电介质层中形成开口并在牺牲电介质层上方和开口中形成铜层。 该方法还包括通过去除牺牲介电层之上的铜层的部分来形成铜互连，从而将铜互连留在开口中。 该方法还包括去除结构之上并邻近铜互连的牺牲电介质层，并在该结构之上形成一个低介电常数介电层，并邻近铜互连。

公开(公告)号：US6107169A

公开(公告)日：2000-08-22

申请号：US134526

申请日：1998-08-14

申请人： Stephen Keetai Park

发明人： Stephen Keetai Park

IPC分类号： H01L21/8247 ,  H01L21/425

CPC分类号： H01L27/11521 ,  Y10S438/923

摘要： In a non-volatile semiconductor memory device, a top surface of a floating gate that is made of polysilicon is advantageously kept smooth to increase the uniformity of an overlying interpoly dielectric layer onto which a control gate is formed. The floating gate is doped after at least a portion of the overlying interpoly dielectric layer has been formed. Ion implantation techniques are employed to implant dopants through the overlying layer or layers and into the floating gate. Consequently, the potential for polysilicon grain growth at or near the top surface of the floating gate, which can lead to significant depressions in the overlying layers and data retention problems in the memory cell, is substantially reduced.

摘要翻译： 在非易失性半导体存储器件中，由多晶硅制成的浮置栅极的顶表面有利地保持平滑，以增加其上形成有控制栅极的上覆多层电介质层的均匀性。 在形成了上覆的多晶硅间介质层的至少一部分之后，浮置栅极被掺杂。 使用离子注入技术来通过上层或多层注入掺杂剂并进入浮栅。 因此，显着降低了可能导致上覆层中的显着凹陷和存储单元中的数据保留问题的浮置栅极顶表面或附近的多晶硅晶粒生长的可能性。