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50 条记录 (耗时 0.019 秒)

    Process of making buried capacitor for silicon-on-insulator structure
    1.
    发明授权
    Process of making buried capacitor for silicon-on-insulator structure 失效
    制造绝缘体上硅结构的埋电容器的工艺

    公开(公告)号：US06337253B1

    公开(公告)日：2002-01-08

    申请号：US09707305

    申请日：2000-11-07

    申请人： Bijan Davari ,  Effendi Leobandung ,  Werner Rausch ,  Ghavam G. Shahidi

    发明人： Bijan Davari ,  Effendi Leobandung ,  Werner Rausch ,  Ghavam G. Shahidi

    IPC分类号： H01L2120

    CPC分类号： H01L29/66181 ,  H01L27/1203

    摘要： A process for making a capacitor for a silicon-on-insulator (SOI) structure. The SOI structure has a p-type silicon base layer, a buried oxide layer, a silicon layer, and an n+ layer formed within a portion of the p-type silicon base layer. The process comprises the steps of forming a buried oxide layer and a silicon layer in the p-type silicon base layer, forming an n+ layer in a portion of the p-type silicon base layer, and forming electrically conductive paths to the p-type silicon base layer and the n+ layer extending through the buried oxide and silicon layers.

    摘要翻译： 一种用于制造绝缘体上硅（SOI）结构的电容器的工艺。 SOI结构具有在p型硅基底层的一部分内形成的p型硅基底层，埋入氧化物层，硅层和n +层。 该工艺包括以下步骤：在p型硅基层中形成掩埋氧化物层和硅层，在p型硅基层的一部分中形成n +层，并形成p型硅基层的导电路径 硅基层和n +层延伸穿过掩埋的氧化物和硅层。

    Buried capacitor for silicon-on-insulator structure
    2.
    发明授权
    Buried capacitor for silicon-on-insulator structure 失效
    埋入式电容器，用于绝缘体上硅结构

    公开(公告)号：US06188122B1

    公开(公告)日：2001-02-13

    申请号：US09231615

    申请日：1999-01-14

    申请人： Bijan Davari ,  Effendi Leobandung ,  Werner Rausch ,  Ghavam G. Shahidi

    发明人： Bijan Davari ,  Effendi Leobandung ,  Werner Rausch ,  Ghavam G. Shahidi

    IPC分类号： H01L2701

    CPC分类号： H01L29/66181 ,  H01L27/1203

    摘要： A process for making a capacitor for a silicon-on-insulator (SOI) structure. The SOI structure has a p-type silicon base layer, a buried oxide layer, a silicon layer, and an n+ layer formed within a portion of the p-type silicon base layer. The process comprises the steps of forming a buried oxide layer and a silicon layer in the p-type silicon base layer, forming an n+ layer in a portion of the p-type silicon base layer, and forming electrically conductive paths to the p-type silicon base layer and the n+ layer extending through the buried oxide and silicon layers.

    摘要翻译： 一种用于制造绝缘体上硅（SOI）结构的电容器的工艺。 SOI结构具有在p型硅基底层的一部分内形成的p型硅基底层，埋入氧化物层，硅层和n +层。 该工艺包括以下步骤：在p型硅基层中形成掩埋氧化物层和硅层，在p型硅基层的一部分中形成n +层，并形成p型硅基层的导电路径 硅基层和n +层延伸穿过掩埋的氧化物和硅层。

    BODY-CONTACTED FINFET
    6.
    发明申请
    BODY-CONTACTED FINFET 有权
    身体接触式FINFET

    公开(公告)号：US20090008705A1

    公开(公告)日：2009-01-08

    申请号：US11773607

    申请日：2007-07-05

    申请人： Huilong Zhu ,  Thomas W. Dyer ,  Jack A. Mandelman ,  Werner Rausch

    发明人： Huilong Zhu ,  Thomas W. Dyer ,  Jack A. Mandelman ,  Werner Rausch

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7842 ,  H01L29/66795 ,  H01L29/785

    摘要： A silicon containing fin is formed on a semiconductor substrate. A silicon oxide layer is formed around the bottom of the silicon containing fin. A gate dielectric is formed on the silicon containing fin followed by formation of a gate electrode. While protecting the portion of the semiconductor fin around the channel, a bottom portion of the silicon containing semiconductor fin is etched by a isotropic etch leaving a body strap between the channel of a finFET on the silicon containing fin and an underlying semiconductor layer underneath the silicon oxide layer. The fin may comprise a stack of inhomogeneous layers in which a bottom layer is etched selectively to a top semiconductor layer. Alternatively, the fin may comprise a homogeneous semiconductor material and the silicon containing fin may be protected by dielectric films on the sidewalls and top surfaces of the silicon containing fin.

    摘要翻译： 在半导体衬底上形成含硅翅片。 在含硅翅片的底部周围形成氧化硅层。 在含硅鳍上形成栅电介质，形成栅电极。 在保护半导体翅片周围的通道的部分的同时，通过各向同性的蚀刻蚀刻含硅半导体鳍片的底部部分，从而在含硅鳍片上的finFET的通道和硅下方的下面的半导体层之间留下体带 氧化层。 翅片可以包括不均匀层的堆叠，其中底层被选择性地蚀刻到顶部半导体层。 或者，翅片可以包括均匀的半导体材料，并且含硅翅片可以由含硅翅片的侧壁和顶表面上的电介质膜保护。

    CMOS circuits including a passive element having a low end resistance
    7.
    发明授权
    CMOS circuits including a passive element having a low end resistance 有权
    CMOS电路包括具有低端电阻的无源元件

    公开(公告)号：US07361959B2

    公开(公告)日：2008-04-22

    申请号：US11164515

    申请日：2005-11-28

    申请人： Christopher D. Sheraw ,  Alyssa C. Bonnoit ,  K. Paul Muller ,  Werner Rausch

    发明人： Christopher D. Sheraw ,  Alyssa C. Bonnoit ,  K. Paul Muller ,  Werner Rausch

    IPC分类号： H01L29/76

    CPC分类号： H01L27/0629 ,  H01L21/26506 ,  H01L28/20 ,  H01L28/40 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits, as well as methods for forming such CMOS circuits. More specifically, the present invention relates to CMOS circuits that contain passive elements, such as buried resistors, capacitors, diodes, inductors, attenuators, power dividers, and antennas, etc., which are characterized by an end contact resistance of less than 90 ohm-microns. Such a low end resistance can be achieved either by reducing the spacer widths of the passive elements to a range of from about 10 nm to about 30 nm, or by masking the passive elements during a pre-amorphization implantation step, so that the passive elements are essentially free of pre-amorphization implants.

    摘要翻译： 本发明涉及互补金属氧化物半导体（CMOS）电路，以及用于形成这种CMOS电路的方法。 更具体地说，本发明涉及包含诸如埋地电阻器，电容器，二极管，电感器，衰减器，功率分配器和天线等无源元件的CMOS电路，其特征在于端接触电阻小于90欧姆 微量元素 这样的低端电阻可以通过将无源元件的间隔物宽度减小到约10nm至约30nm的范围，或通过在预非晶化注入步骤期间掩蔽无源元件来实现，使得无源元件 基本上没有前非晶化植入物。

    ULTRA SHALLOW JUNCTION FORMATION BY EPITAXIAL INTERFACE LIMITED DIFFUSION
    8.
    发明申请
    ULTRA SHALLOW JUNCTION FORMATION BY EPITAXIAL INTERFACE LIMITED DIFFUSION 有权
    通过外延界面有限扩散形成的超声结构

    公开(公告)号：US20060076627A1

    公开(公告)日：2006-04-13

    申请号：US10711899

    申请日：2004-10-12

    申请人： Huajie Chen ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Werner Rausch

    发明人： Huajie Chen ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Werner Rausch

    IPC分类号： H01L29/94

    CPC分类号： H01L21/26533 ,  H01L21/02238 ,  H01L21/26513 ,  H01L21/31654 ,  H01L21/31675 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/66636

    摘要： A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.

    摘要翻译： 形成场效应晶体管的方法产生更浅和更尖的结，同时在与当前制造技术一致的工艺中最大化掺杂剂活化。 更具体地，本发明增加了硅衬底的顶表面的氧含量。 优选在增加硅衬底的顶表面的氧含量之前清洁硅衬底的顶表面。 硅衬底的顶表面的氧含量高于硅衬底的其它部分，但低于防止外延生长的量。 这允许本发明在硅​​衬底的顶表面上外延生长硅层。 此外，增加的氧含量基本上限制外延硅层内的掺杂剂移动到硅衬底中。

    METHOD OF MANUFACTURE OF RAISED SOURCE DRAIN MOSFET WITH TOP NOTCHED GATE STRUCTURE FILLED WITH DIELECTRIC PLUG IN AND DEVICE MANUFACTURED THEREBY
    10.
    发明申请
    METHOD OF MANUFACTURE OF RAISED SOURCE DRAIN MOSFET WITH TOP NOTCHED GATE STRUCTURE FILLED WITH DIELECTRIC PLUG IN AND DEVICE MANUFACTURED THEREBY 审中-公开
    具有插入电介质插入件的顶部注入栅结构的放大源漏MOSFET的制造方法及其制造方法

    公开(公告)号：US20050054169A1

    公开(公告)日：2005-03-10

    申请号：US10605100

    申请日：2003-09-09

    申请人： Tina Wagner ,  Werner Rausch ,  Sadanand Deshpande

    发明人： Tina Wagner ,  Werner Rausch ,  Sadanand Deshpande

    IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/331

    CPC分类号： H01L29/66772 ,  H01L29/78618

    摘要： A method is provided for forming an SOI MOSFET device with a silicon layer formed on a dielectric layer with a gate electrode stack, with sidewall spacers on sidewalls of the gate electrode stack and raised source/drain regions formed on the surface of the silicon layer. The gate electrode stack comprises a gate electrode formed of polysilicon over a gate dielectric layer formed on the surface of the silicon layer. A plug of dielectric material is formed in a notch in a cap layer above the gate polysilicon. The sidewalls of the gate electrode is covered by the sidewall spacers which cover a portion of the plug for the purpose of eliminating the exposure of the gate polysilicon so that formation of spurious epitaxial growth during the formation of raised source/drain regions is avoided.

    摘要翻译： 提供了一种用于形成具有形成在具有栅极电极堆叠的电介质层上的硅层的SOI MOSFET器件的方法，在栅电极堆叠的侧壁上具有侧壁间隔物，并且形成在硅层的表面上的升高的源极/漏极区域。 栅极电极堆叠包括在形成于硅层的表面上的栅极电介质层上的多晶硅形成的栅电极。 在栅多晶硅上方的帽层中的凹口中形成介电材料塞。 为了消除栅极多晶硅的暴露，覆盖一部分插塞的侧壁间隔物覆盖栅电极的侧壁，从而避免在形成升高的源极/漏极区域期间形成假外延生长。