公开(公告)号：US20080040765A1

公开(公告)日：2008-02-14

申请号：US11838064

申请日：2007-08-13

申请人： Peter Bradshaw ,  Wei Wang ,  Paul Ta ,  Bill Tang ,  Alvin Wang

发明人： Peter Bradshaw ,  Wei Wang ,  Paul Ta ,  Bill Tang ,  Alvin Wang

IPC分类号： H04N7/173

CPC分类号： H04L5/16 ,  H04L69/324

摘要： A method provides a bidirectional communication protocol for data communication between a first device and a second device. The method includes: during a first time interval, transmitting data from the first device to the second device; and during a second time interval, (a) after the occurrence of a first event, (i) suspending data transmission from the first device to the second device; and (ii) transmitting control data from the second device to the first device; and (b) after the occurrence of a second event, transmitting control data from the first device to the second device.

摘要翻译： 一种方法提供用于第一设备和第二设备之间的数据通信的双向通信协议。 该方法包括：在第一时间间隔期间，将数据从第一设备发送到第二设备; 并且在第二时间间隔期间，（a）在发生第一事件之后，（i）暂停从第一设备到第二设备的数据传输; 和（ii）将控制数据从第二设备发送到第一设备; 和（b）在第二事件发生之后，将控制数据从第一设备发送到第二设备。

公开(公告)号：US20080037617A1

公开(公告)日：2008-02-14

申请号：US11838069

申请日：2007-08-13

申请人： Bill Tang ,  Paul Ta

发明人： Bill Tang ,  Paul Ta

IPC分类号： H04B1/38 ,  H04L5/16

CPC分类号： H04L25/0276 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45632 ,  H03F2203/45101 ,  H03F2203/45138 ,  H03F2203/45418 ,  H03F2203/45466 ,  H03F2203/45681

摘要： In a transceiver, a transmitter circuit is provided substantially the same common-mode voltage regardless of whether the transceiver is in a transmitting or receiving mode. In one embodiment, the transmitter circuit includes a driver circuit which, in the transmission mode of the transceiver, drives an output differential signal, and which, in the receiving mode of the transceiver, provides a termination circuit for an input differential signal. A variable resistor is provided to connect between a supply voltage and the driver circuit, the resistance of the variable resistor is selected such that the common-mode voltage of the output differential signal of the transmission mode substantially equals the common-mode voltage in the input differential signal of the receiving mode.

摘要翻译： 在收发器中，发射机电路提供基本上相同的共模电压，而不管收发器是处于发送还是接收模式。 在一个实施例中，发射机电路包括在收发器的传输模式下驱动输出差分信号的驱动器电路，以及在收发器的接收模式下，为输入差分信号提供终端电路。 提供可变电阻器以连接电源电压和驱动器电路之间，选择可变电阻器的电阻，使得传输模式的输出差分信号的共模电压基本上等于输入中的共模电压 接收模式的差分信号。

公开(公告)号：US20080037613A1

公开(公告)日：2008-02-14

申请号：US11838084

申请日：2007-08-13

申请人： Paul Ta ,  Wei Wang ,  Alvin Wang ,  Peter Bradshaw

发明人： Paul Ta ,  Wei Wang ,  Alvin Wang ,  Peter Bradshaw

IPC分类号： H04B1/69

CPC分类号： H04B15/04 ,  H04B2215/067

摘要： A spread spectrum clock signal generator and an accompanying method provide a spread spectrum clock signal of a reduced electromagnetic interference. The spread spectrum clock signal generator includes (a) a state machine, which maintains a current state of the spread spectrum clock signal generator, receives as input value a next state of the spread spectrum clock signal generator and generates a clock phase selection signal based on the current and next states; (b) a random number generator for generating the next state; and (c) a waveform generation circuit for generating a spread spectrum clock signal based on the clock phase selection signal.

摘要翻译： 扩频时钟信号发生器和伴随方法提供了降低的电磁干扰的扩频时钟信号。 扩展频谱时钟信号发生器包括：（a）保持扩频时钟信号发生器的当前状态的状态机接收扩频时钟信号发生器的下一个状态作为输入值，并产生基于 当前和下一个州; （b）用于产生下一状态的随机数发生器; 和（c）用于基于时钟相位选择信号产生扩频时钟信号的波形发生电路。

公开(公告)号：US06222353B1

公开(公告)日：2001-04-24

申请号：US09583325

申请日：2000-05-31

申请人： Srinivas Pattamatta ,  Paul Ta

发明人： Srinivas Pattamatta ,  Paul Ta

IPC分类号： G05F140

CPC分类号： G05F1/465 ,  G05F1/575 ,  Y10S323/901

摘要： The performance of the main regulatory transistor of an on-chip voltage regulator circuit is enhanced when the main transistor is appropriately biased during start up. In an example embodiment, a voltage regulator circuit includes a thin gate oxide transistor as the main regulatory transistor and an operational amplifier that is referenced to a midlevel operating voltage. During start-up, the potential voltage difference is large enough to necessitate the disconnection of the main transistor from the operational amplifier. A voltage divider ladder circuit is used to maintain the gate voltage of the main transistor at the midlevel voltage while a smaller thick gate oxide transistor is used to maintain loop stability and to withstand voltage transients.

公开(公告)号：US08363705B2

公开(公告)日：2013-01-29

申请号：US13211915

申请日：2011-08-17

申请人： Bill R-S Tang ,  Paul Ta

发明人： Bill R-S Tang ,  Paul Ta

IPC分类号： H04B1/38

CPC分类号： H04L25/0276 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45632 ,  H03F2203/45101 ,  H03F2203/45138 ,  H03F2203/45418 ,  H03F2203/45466 ,  H03F2203/45681

摘要： In a transceiver, a transmitter circuit is provided substantially the same common-mode voltage regardless of whether the transceiver is in a transmitting or receiving mode. In one embodiment, the transmitter circuit includes a driver circuit which, in the transmission mode of the transceiver, drives an output differential signal, and which, in the receiving mode of the transceiver, provides a termination circuit for an input differential signal. A variable resistor is provided to connect between a supply voltage and the driver circuit, the resistance of the variable resistor is selected such that the common-mode voltage of the output differential signal of the transmission mode substantially equals the common-mode voltage in the input differential signal of the receiving mode.

摘要翻译： 在收发器中，发射机电路提供基本上相同的共模电压，而不管收发器是处于发送还是接收模式。 在一个实施例中，发射机电路包括在收发器的传输模式下驱动输出差分信号的驱动器电路，以及在收发器的接收模式下，为输入差分信号提供终端电路。 提供可变电阻器以连接电源电压和驱动器电路之间，选择可变电阻器的电阻，使得传输模式的输出差分信号的共模电压基本上等于输入中的共模电压 接收模式的差分信号。

公开(公告)号：US20110038286A1

公开(公告)日：2011-02-17

申请号：US12773115

申请日：2010-05-04

申请人： Paul Ta ,  Wei Wang

发明人： Paul Ta ,  Wei Wang

IPC分类号： H04L5/14 ,  H04Q11/02

CPC分类号： H04Q11/02 ,  H04B2203/5483 ,  H04L1/16 ,  H04Q2213/13036 ,  H04Q2213/13175 ,  H04Q2213/1332

摘要： A system comprising a first serializer/deserializer coupled to a first electronic device and a second serializer/deserializer couple to a second electronic device is provided. The first serializer/deserializer comprises a forward channel driver and the second serializer/deserializer comprises a reverse channel driver. A communication medium is coupled between the first and second serializer/deserializers, and the first and second serializer/deserializers are AC coupled to the communication medium to provide a high frequency forward channel and are DC coupled to the communication medium to provide a low frequency reverse channel.

摘要翻译： 提供了一种包括耦合到第一电子设备的第一串行器/解串器和到第二电子设备的第二串行器/解串器耦合的系统。 第一串行器/解串器包括前向通道驱动器，第二串行器/解串器包括反向通道驱动器。 通信介质耦合在第一和第二串行器/解串行器之间，并且第一和第二串行器/解串行器被AC耦合到通信介质以提供高频率前向信道，并且被直流耦合到通信介质以提供低频反向 渠道。

公开(公告)号：US20070279408A1

公开(公告)日：2007-12-06

申请号：US11446488

申请日：2006-06-01

申请人： Dong Zheng ,  Paul Ta ,  Roger Levinson

发明人： Dong Zheng ,  Paul Ta ,  Roger Levinson

IPC分类号： G09G5/00 ,  H04L12/28

CPC分类号： G09G5/006 ,  G09G2370/047 ,  H04N7/108 ,  H04N21/2365 ,  H04N21/4305 ,  H04N21/4347

摘要： Multiple data streams are distributed using conventional data cables and multiplexing circuits by taking advantage of a technique that allows reliable high speed transmission of digital data. In one example, a number of parallel data streams (e.g., video data streams) are serialized to allow them to be economically and reliably transmitted over conventional data cables (e.g., category 5 or category 6 twisted pair cables, and automotive data transmission cables) over long distance. The parallel data streams are recovered by deserializing from the transmitted signal using a data recovery technique that recovers a clocking signal from the transmitted signal. In another example, multiple data streams from multiple asynchronous sources are multiplexed to provide an input data stream to a display device. The multiple data stream may be provided through, for example, conventional connection cables (e.g., DVI, LEONI, CATS or CAT6 cables).

摘要翻译： 通过利用允许数字数据的可靠高速传输的技术，使用传统的数据电缆和多路复用电路来分配多个数据流。 在一个示例中，将多个并行数据流（例如，视频数据流）串行化以允许它们通过常规数据电缆（例如，类别5或类别6双绞线电缆和汽车数据传输电缆）经济地和可靠地传输， 远距离。 并行数据流通过使用从发送信号中恢复时钟信号的数据恢复技术从发送信号反序列化而被恢复。 在另一示例中，来自多个异步源的多个数据流被多路复用以向显示设备提供输入数据流。 多数据流可以通过例如常规连接电缆（例如，DVI，LEONI，CATS或CAT6电缆）来提供。

公开(公告)号：US06380721B1

公开(公告)日：2002-04-30

申请号：US09783478

申请日：2001-02-14

申请人： Srinivas Pattamatta ,  Paul Ta

发明人： Srinivas Pattamatta ,  Paul Ta

IPC分类号： G05F140

摘要： The performance of the main regulatory transistor of an on-chip voltage regulator circuit is enhanced when the main transistor is appropriately biased during start up. In an example embodiment, a voltage regulator circuit includes a thin gate oxide transistor as the main regulatory transistor and an operational amplifier that is referenced to a midlevel operating voltage. During start-up, the potential voltage difference is large enough to necessitate the disconnection of the main transistor from the operational amplifier. A voltage divider ladder circuit is used to maintain the gate voltage of the main transistor at the midlevel voltage while a smaller thick gate oxide transistor is used to maintain loop stability and to withstand voltage transients.

公开(公告)号：US5608357A

公开(公告)日：1997-03-04

申请号：US526956

申请日：1995-09-12

申请人： Paul Ta ,  Michael Cheng

发明人： Paul Ta ,  Michael Cheng

IPC分类号： H03K3/03 ,  H03K3/354 ,  H03L7/099 ,  H03L7/10 ,  H04J3/06 ,  H04L7/033 ,  H03B5/24 ,  H04L7/00 ,  H04L25/36

CPC分类号： H03L7/0805 ,  H03K3/03 ,  H03K3/354 ,  H03L7/0995 ,  H03L7/10 ,  H04J3/0626 ,  H04L7/005 ,  H04L7/0337

摘要： A data retiming system for retiming incoming data and eliminating jitter is described. The data retiming system includes a local clock; a phase aligner for receiving the incoming data and producing a recovered clock from the incoming data, and then producing retimed incoming data by retiming the incoming data with the recovered clock; and a buffer memory for removing jitter from the retimed incoming data by storing the retimed incoming data to the buffer memory in accordance with the recovered clock and reading the stored data from the buffer memory in accordance with the local clock. The data retiming system provides reliable operation even at very high data rates. A freezeable voltage-controlled oscillator for producing a clock signal in accordance with a freeze signal and a frequency control signal is also disclosed. Using current steering techniques, the freezeable voltage-controlled oscillator is able to freeze its output very quickly.

摘要翻译： 描述了重新定时输入数据并消除抖动的数据重新定时系统。 数据重定时系统包括本地时钟; 相位对准器，用于接收输入数据并从输入数据产生恢复的时钟，然后通过用恢复的时钟重新定时输入数据来产生重新定时的输入数据; 以及缓冲存储器，用于根据恢复的时钟将重新定时的进入数据存储到缓冲存储器，并根据本地时钟从缓冲存储器读取存储的数据，从重定时输入数据中去除抖动。 数据重定时系统即使在非常高的数据速率下也能提供可靠的操作。 还公开了一种用于根据冻结信号和频率控制信号产生时钟信号的可冻结压控振荡器。 使用当前的转向技术，可冻结压控振荡器能够非常快地冻结其输出。