公开(公告)号：US06535424B2

公开(公告)日：2003-03-18

申请号：US09915018

申请日：2001-07-25

申请人： Binh Q. Le ,  Masaru Yano ,  Santosh K. Yachareni

发明人： Binh Q. Le ,  Masaru Yano ,  Santosh K. Yachareni

IPC分类号： G11C1604

CPC分类号： G11C16/08 ,  G11C8/08

摘要： Flash memory array systems and methods are disclosed for producing a supply regulated boost voltage, wherein the application of a supply voltage to a supply voltage level detection circuit (e.g., analog to digital converter, digital thermometer) which is used to generating one or more supply voltage level detection signals from measurement of the supply voltage level applied to the voltage boost circuit, which may be used as a boosted wordline voltage for the read mode operations of programmed memory cells, and wherein the supply voltage level detection signals are applied to a boosted voltage compensation circuit to generate one or more boosted voltage compensation signals which are applied to a voltage boost circuit operable to generate a regulated boosted voltage for a flash memory array of programmed core cells. Thus, a fast compensation means is disclosed for the VCC power supply variations typically reflected in the output of the boost voltage circuit supplied to the word line of the flash memory array, thereby generating wordline voltages during the read mode which are substantially independent of variations in the supply voltage.

摘要翻译： 闪存阵列系统和方法被公开用于产生电源调节升压电压，其中将电源电压施加到用于产生一个或多个电源的电源电压电平检测电路（例如，模数转换器，数字温度计） 电压电平检测信号来自测量施加到升压电路的电源电压电平，其可以用作用于编程存储器单元的读取模式操作的升压字线电压，并且其中电源电压电平检测信号被施加到升压 电压补偿电路以产生一个或多个升压电压补偿信号，所述升压电压补偿信号被施加到升压电路，所述升压电路可操作以产生用于编程核心单元的闪存阵列的调节升压电压。 因此，公开了一种快速补偿装置，用于通常反映在提供给闪速存储器阵列的字线的升压电压电路的输出中的VCC电源变化，从而在读取模式期间产生字线电压，其基本上与 电源电压。

公开(公告)号：US08705303B2

公开(公告)日：2014-04-22

申请号：US13413527

申请日：2012-03-06

申请人： Akira Ogawa ,  Masaru Yano

发明人： Akira Ogawa ,  Masaru Yano

IPC分类号： G11C7/00

CPC分类号： H01L27/1052 ,  G11C16/0466 ,  G11C16/28 ,  Y10T29/41

摘要： The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.

摘要翻译： 本发明提供一种半导体存储器及其控制方法，所述半导体器件包括连接到设置在非易失性存储单元阵列中的核心单元的第一电流 - 电压转换电路，连接到参考单元的第二电流 - 电压转换电路 参考单元数据线，感测来自第一电流 - 电压转换电路的输出和来自第二电流 - 电压转换电路的输出的读出放大器，将参考单元数据线上的电压电平与预定电压电平进行比较的比较电路 以及如果在对所述参考单元数据线预充电期间所述参考单元数据线处的电压电平低于所述预定电压电平，则对所述参考单元数据线充电的充电电路。 根据本发明，可以缩短参考单元数据线的预充电周期，并且可以缩短数据读取时间。

公开(公告)号：US08351268B2

公开(公告)日：2013-01-08

申请号：US13253634

申请日：2011-10-05

申请人： Akira Ogawa ,  Masaru Yano

发明人： Akira Ogawa ,  Masaru Yano

IPC分类号： G11C11/34

CPC分类号： H01L27/1052 ,  G11C16/0466 ,  G11C16/28 ,  Y10T29/41

摘要： The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.

公开(公告)号：US20110032764A1

公开(公告)日：2011-02-10

申请号：US12905716

申请日：2010-10-15

申请人： Akira Ogawa ,  Masaru Yano

发明人： Akira Ogawa ,  Masaru Yano

IPC分类号： G11C16/28 ,  G11C16/04

CPC分类号： H01L27/1052 ,  G11C16/0466 ,  G11C16/28 ,  Y10T29/41

摘要： The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a reference cell data line (24), a sense amplifier (18) sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit (28) comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit (30) charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.

摘要翻译： 本发明提供一种半导体存储器及其控制方法，所述半导体器件包括连接到设置在非易失性存储单元阵列（10）中的核心单元（12）的第一电流 - 电压转换电路（16），第二电流 - 电压转换电路（26），通过参考单元数据线（24）连接到参考单元（22）;感测放大器（18），感测来自第一电流 - 电压转换电路的输出和来自第二电流电压 转换电路，将参考单元数据线上的电压电平与预定电压电平进行比较的比较电路（28）以及对参考单元数据线充电的充电电路（30），如果参考单元数据线上的电压电平为 在预充电参考单元数据线期间低于预定电压电平。 根据本发明，可以缩短参考单元数据线的预充电周期，并且可以缩短数据读取时间。

公开(公告)号：US20070183193A1

公开(公告)日：2007-08-09

申请号：US11639128

申请日：2006-12-13

申请人： Masaru Yano ,  Hideki Arakawa ,  Mototada Sakashita ,  Akira Ogawa ,  Yoshiaki Shinmura ,  Hajime Aoki

发明人： Masaru Yano ,  Hideki Arakawa ,  Mototada Sakashita ,  Akira Ogawa ,  Yoshiaki Shinmura ,  Hajime Aoki

IPC分类号： G11C16/06 ,  G11C11/34

CPC分类号： G11C16/0475

摘要： A control method for a nonvolatile storage device having a storage mode in which in a memory cell provided with a trapping dielectric layer 1-bit data is stored depending on the presence or absence of charge in a first trapping region. In a dynamic reference cell initialization operation, a charge accumulation operation is performed, as a preset operation in the initialization operation, on second trapping regions of first and second dynamic reference cells to a charge accumulation operation on a second trapping region of the memory cell. In addition, at the time of data rewrite, preprogram verification and preprogramming are performed on the first trapping regions. This makes it possible to shorten the time taken for initialization and data rewrite.

摘要翻译： 一种具有存储模式的非易失性存储装置的控制方法，其中根据在第一捕获区域中是否存在电荷而存储具有捕获电介质层1位数据的存储单元。 在动态参考单元初始化操作中，作为初始化操作中的预设操作，在第一和第二动态参考单元的第二陷印区域上执行电荷累积操作，以对存储单元的第二陷印区域进行电荷累积操作。 此外，在数据重写时，对第一捕获区域执行预编程验证和预编程。 这使得可以缩短初始化和数据重写所花费的时间。

公开(公告)号：US20060215477A1

公开(公告)日：2006-09-28

申请号：US11290001

申请日：2005-11-30

申请人： Masaru Yano ,  Hiroki Murakami

发明人： Masaru Yano ,  Hiroki Murakami

IPC分类号： G11C8/00

CPC分类号： G11C16/0466 ,  G11C16/0483 ,  G11C16/26

摘要： A semiconductor device includes: memory blocks each having groups of memory cells that are connected to word lines; select gates for selecting the groups of memory cells; and an apply circuit that applies, at the time of reading data, a back bias to the select gates of unselected memory blocks.

摘要翻译： 半导体器件包括：各自具有连接到字线的存储器单元组的存储器块; 选择用于选择存储器单元组的门; 以及在读取数据时向未选择的存储块的选择栅极施加反向偏置的施加电路。

公开(公告)号：US06925005B2

公开(公告)日：2005-08-02

申请号：US10647441

申请日：2003-08-26

申请人： Shoichi Kawamura ,  Masaru Yano ,  Makoto Niimi ,  Kenji Nagai

发明人： Shoichi Kawamura ,  Masaru Yano ,  Makoto Niimi ,  Kenji Nagai

IPC分类号： G11C16/06 ,  G11C5/00 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/3436

摘要： The present invention is a memory circuit, comprises: a memory cell array including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells disposed in the positions of intersection between the bit lines and the word lines; and a page buffer, which is connected to the bit line and which detects memory cell data by judging with predetermined sense timing the potential of the bit line when a pre-charged bit line potential is discharged in accordance to a cell current of a selected memory cell. Further the sense timing differs in accordance with the position of the selected memory cell in the memory cell array.

摘要翻译： 本发明是一种存储器电路，包括：存储单元阵列，包括多个位线，多个字线以及设置在位线和字线之间的交叉位置的多个存储单元; 以及页缓冲器，其连接到位线，并且通过根据所选择的存储器的单元电流在预充电位线电位被放电时，用预定的感测定时判断位线的电位来检测存储单元数据 细胞。 此外，感测定时根据存储单元阵列中所选存储单元的位置而不同。

公开(公告)号：US06738287B2

公开(公告)日：2004-05-18

申请号：US10438211

申请日：2003-05-15

申请人： Masaru Yano

发明人： Masaru Yano

IPC分类号： G11C1604

CPC分类号： G11C16/3459 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3481

摘要： A nonvolatile semiconductor memory device includes a memory core circuit which is nonvolatile and stores multi-values therein by setting different thresholds to memory cells, and a control circuit which controls data writing into the memory core circuit, wherein the control circuit programs first memory cells to be at one of the thresholds by setting the one of the thresholds not only to the first memory cells but also to second memory cells that are subsequently to be programmed to any one of the thresholds higher than the one of the thresholds, the control circuit successively performing programming in an ascending order of the thresholds.

摘要翻译： 非易失性半导体存储器件包括：非易失性存储器核心电路，通过对存储单元设置不同的阈值来存储多个值;以及控制电路，其将数据写入到存储器核心电路中，其中控制电路将第一存储器单元 通过将阈值中的一个不仅设置到第一存储器单元，而且将第二存储器单元设置为高于阈值中的任一阈值的第二存储器单元，控制电路连续地处于阈值之一 以阈值的升序执行编程。

公开(公告)号：US06622230B1

公开(公告)日：2003-09-16

申请号：US09724675

申请日：2000-11-28

申请人： Masaru Yano ,  Shane Hollmer ,  Michael Chung

发明人： Masaru Yano ,  Shane Hollmer ,  Michael Chung

IPC分类号： G06F1206

CPC分类号： G11C16/08 ,  G11C16/16

摘要： A method is provided for selecting a group of memory blocks in a flash memory device given their starting and ending addresses. The method compares the two addresses to determine the multi-block first bit location which is the most significant bit location where the starting and ending addresses have different bits. The method then generates a converted memory block address where bits more significant than the multi-block first bit location are the ending address bits and where bits less significant than, or equal in significance to, the multi-block first bit location are equal to a logic 1. The method also generates a converted complementary memory block address identical to the other converted address except that bits in the bit locations more significant than the multi-block first bit location are the complements of the ending address bits. The method then pre-decodes the two converted addresses to generate sets of pre-decoded z-signals corresponding to the block addresses included in a group of the starting and ending addresses and all the addresses between them. Finally, the method decodes the pre-decoded z-signals to generate signals selecting memory blocks whose addresses are in that group.

摘要翻译： 提供了一种用于在给定其起始和结束地址的情况下选择闪存设备中的一组存储器块的方法。 该方法比较两个地址以确定作为开始和结束地址具有不同位的最高有效位位置的多块第一位位置。 该方法然后产生转换的存储器块地址，其中比多块第一位位置更重要的位是结束地址位，并且其中比多块第一位位置更少显着性或相当于其的位等于 该方法还生成与其它转换地址相同的转换的补充存储器块地址，除了比多块第一位位置更重要的位位置的位是结束地址位的补码。 然后，该方法对两个转换的地址进行预解码，以生成与包括在起始地址和结束地址的组中的块地址相对应的预解码z信号的集合以及它们之间的所有地址。 最后，该方法对预解码的z信号进行解码以产生选择地址在该组中的存储块的信号。

公开(公告)号：US5978267A

公开(公告)日：1999-11-02

申请号：US175647

申请日：1998-10-20

申请人： Pau-Ling Chen ,  Michael Van Buskirk ,  Shane C. Hollmer ,  Michael S. C. Chung ,  Binh Quang Le ,  Vincent Leung ,  Shoichi Kawamura ,  Masaru Yano

发明人： Pau-Ling Chen ,  Michael Van Buskirk ,  Shane C. Hollmer ,  Michael S. C. Chung ,  Binh Quang Le ,  Vincent Leung ,  Shoichi Kawamura ,  Masaru Yano

IPC分类号： G11C16/02 ,  G11C7/12 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C7/12

摘要： In the programming of a non-volatile memory device, such as a NAND flash memory device 100, a positive bias voltage V.sub.bias is applied to a bit line 44 to set a respective memory gate 44a in a programmed state. In a further embodiment, the positive bias voltage V.sub.bias is obtained by dividing the select drain gate voltage V.sub.cc using two resistors 56 and 58 connected in series.

摘要翻译： 在非易失性存储器件（例如NAND闪速存储器件100）的编程中，将正偏置电压Vbias施加到位线44以将相应的存储器栅极44a设置为编程状态。 在另一实施例中，通过使用串联连接的两个电阻器56和58分压选择漏极栅极电压Vcc来获得正偏置电压Vbias。