公开(公告)号：US06925005B2

公开(公告)日：2005-08-02

申请号：US10647441

申请日：2003-08-26

申请人： Shoichi Kawamura ,  Masaru Yano ,  Makoto Niimi ,  Kenji Nagai

发明人： Shoichi Kawamura ,  Masaru Yano ,  Makoto Niimi ,  Kenji Nagai

IPC分类号： G11C16/06 ,  G11C5/00 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/3436

摘要： The present invention is a memory circuit, comprises: a memory cell array including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells disposed in the positions of intersection between the bit lines and the word lines; and a page buffer, which is connected to the bit line and which detects memory cell data by judging with predetermined sense timing the potential of the bit line when a pre-charged bit line potential is discharged in accordance to a cell current of a selected memory cell. Further the sense timing differs in accordance with the position of the selected memory cell in the memory cell array.

摘要翻译： 本发明是一种存储器电路，包括：存储单元阵列，包括多个位线，多个字线以及设置在位线和字线之间的交叉位置的多个存储单元; 以及页缓冲器，其连接到位线，并且通过根据所选择的存储器的单元电流在预充电位线电位被放电时，用预定的感测定时判断位线的电位来检测存储单元数据 细胞。 此外，感测定时根据存储单元阵列中所选存储单元的位置而不同。

公开(公告)号：US06738288B2

公开(公告)日：2004-05-18

申请号：US10459427

申请日：2003-06-12

申请人： Shoichi Kawamura ,  Masaru Yano

发明人： Shoichi Kawamura ,  Masaru Yano

IPC分类号： G11C1600

CPC分类号： G11C16/105 ,  G11C8/12 ,  G11C16/10 ,  G11C16/102 ,  G11C2216/14

摘要： A nonvolatile semiconductor memory with a plurality of banks in which copy back is performed between banks. An input circuit accepts input of a copy back command which requests a data transfer in the memory. When the copy back command is input from the input circuit, a judgment circuit judges whether a source and a destination are in the same bank. If the judgment circuit judges that the source and the destination are in the same bank, a first transfer circuit transfers data in the same bank. If the judgment circuit judges that the source and the destination are in different banks, a second transfer circuit transfers data between the two different banks.

摘要翻译： 具有多个银行的非易失性半导体存储器，其中在存储体之间执行复制。 输入电路接受请求数据在存储器中传输的复制命令的输入。 当从输入电路输入复制命令时，判断电路判断源和目的地是否在同一个存储体中。 如果判断电路判定源和目的地在同一个存储体中，则第一传送电路在同一个存储体中传送数据。 如果判断电路判定源和目的地在不同的存储体中，则第二传送电路在两个不同的存储体之间传送数据。

公开(公告)号：US5978267A

公开(公告)日：1999-11-02

申请号：US175647

申请日：1998-10-20

申请人： Pau-Ling Chen ,  Michael Van Buskirk ,  Shane C. Hollmer ,  Michael S. C. Chung ,  Binh Quang Le ,  Vincent Leung ,  Shoichi Kawamura ,  Masaru Yano

发明人： Pau-Ling Chen ,  Michael Van Buskirk ,  Shane C. Hollmer ,  Michael S. C. Chung ,  Binh Quang Le ,  Vincent Leung ,  Shoichi Kawamura ,  Masaru Yano

IPC分类号： G11C16/02 ,  G11C7/12 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C7/12

摘要： In the programming of a non-volatile memory device, such as a NAND flash memory device 100, a positive bias voltage V.sub.bias is applied to a bit line 44 to set a respective memory gate 44a in a programmed state. In a further embodiment, the positive bias voltage V.sub.bias is obtained by dividing the select drain gate voltage V.sub.cc using two resistors 56 and 58 connected in series.

摘要翻译： 在非易失性存储器件（例如NAND闪速存储器件100）的编程中，将正偏置电压Vbias施加到位线44以将相应的存储器栅极44a设置为编程状态。 在另一实施例中，通过使用串联连接的两个电阻器56和58分压选择漏极栅极电压Vcc来获得正偏置电压Vbias。

公开(公告)号：US5852576A

公开(公告)日：1998-12-22

申请号：US944904

申请日：1997-10-06

申请人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Charles Hollmer ,  Shoichi Kawamura ,  Michael Shingche Chung ,  Vincent C. Leung ,  Masaru Yano

发明人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Charles Hollmer ,  Shoichi Kawamura ,  Michael Shingche Chung ,  Vincent C. Leung ,  Masaru Yano

IPC分类号： G11C16/06 ,  G11C8/08 ,  G11C16/12 ,  G11C13/00

CPC分类号： G11C16/12 ,  G11C8/08

摘要： Two NMOS boost transistors have their sources connected to the high voltage input while their drains and gates are cross-connected. Two coupling capacitors connect two alternate phase clocks to the gates of the two cross-connected boost transistors. An NMOS pass transistor has its gate connected to the drain of one of the NMOS boost transistors, its source connected to the high voltage input, and its drain connected to the output. In an embodiment, two diode-connected regulation transistors connect the gates of the boost transistors to the high voltage input. These connections insure that the gates of the boost transistors and the gate of the pass transistor never reach voltages higher than one threshold voltage above the high voltage input. In another embodiment, two discharge transistors have their drains connected to a decode input, their sources connected to the gates of the boost transistors, and their gates connected to the positive power supply. By setting the decode input at zero volts, the voltages at the gates of the boost transistors and of the pass transistor are held at zero volts, thus disabling them. In the preferred embodiment, both the regulation transistors and the discharge transistors are included in the high voltage pass gate.

摘要翻译： 两个NMOS升压晶体管的源极连接到高压输入端，而它们的漏极和栅极交叉连接。 两个耦合电容器将两个交替相位时钟连接到两个交叉连接的升压晶体管的栅极。 NMOS传输晶体管的栅极连接到一个NMOS升压晶体管的漏极，其源极连接到高压输入，其漏极连接到输出。 在一个实施例中，两个二极管连接的调节晶体管将升压晶体管的栅极连接到高电压输入。 这些连接确保升压晶体管的栅极和传输晶体管的栅极不会达到高于高电压输入以上的一个阈值电压的电压。 在另一个实施例中，两个放电晶体管的漏极连接到解码输入，其源极连接到升压晶体管的栅极，并且其栅极连接到正电源。 通过将解码输入设置为零伏特，升压晶体管和传输晶体管的栅极处的电压保持在零伏特，从而禁止它们。 在优选实施例中，调节晶体管和放电晶体管都包括在高压通栅中。

公开(公告)号：US5801579A

公开(公告)日：1998-09-01

申请号：US808237

申请日：1997-02-28

申请人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Hollmer ,  Shoichi Kawamura ,  Michael Chung ,  Vincent Leung ,  Masaru Yano

发明人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Hollmer ,  Shoichi Kawamura ,  Michael Chung ,  Vincent Leung ,  Masaru Yano

IPC分类号： G11C8/08 ,  G11C16/12 ,  G05F1/10

CPC分类号： G11C16/12 ,  G11C8/08

摘要： Two NMOS boost transistors have their sources connected to the high voltage input while their drains and gates are cross-connected. Two coupling capacitors connect two alternate phase clocks to the gates of the two cross-connected boost transistors. An NMOS pass transistor has its gate connected to the drain of one of the NMOS boost transistors, its source connected to the high voltage input, and its drain connected to the output. In an embodiment, two diode-connected regulation transistors connect the gates of the boost transistors to the high voltage input. These connections insure that the gates of the boost transistors and the gate of the pass transistor never reach voltages higher than one threshold voltage above the high voltage input. In another embodiment, two discharge transistors have their drains connected to a decode input, their sources connected to the gates of the boost transistors, and their gates connected to the positive power supply. By setting the decode input at zero volts, the voltages at the gates of the boost transistors and of the pass transistor are held at zero volts, thus disabling them. In the preferred embodiment, both the regulation transistors and the discharge transistors are included in the high voltage pass gate.

摘要翻译： 两个NMOS升压晶体管的源极连接到高压输入端，而它们的漏极和栅极交叉连接。 两个耦合电容器将两个交替相位时钟连接到两个交叉连接的升压晶体管的栅极。 NMOS传输晶体管的栅极连接到一个NMOS升压晶体管的漏极，其源极连接到高压输入，其漏极连接到输出。 在一个实施例中，两个二极管连接的调节晶体管将升压晶体管的栅极连接到高电压输入。 这些连接确保升压晶体管的栅极和传输晶体管的栅极不会达到高于高电压输入以上的一个阈值电压的电压。 在另一个实施例中，两个放电晶体管的漏极连接到解码输入，其源极连接到升压晶体管的栅极，并且其栅极连接到正电源。 通过将解码输入设置为零伏特，升压晶体管和传输晶体管的栅极处的电压保持在零伏特，从而禁止它们。 在优选实施例中，调节晶体管和放电晶体管都包括在高压通栅中。

公开(公告)号：US08040730B2

公开(公告)日：2011-10-18

申请号：US12625723

申请日：2009-11-25

申请人： Masahito Takehara ,  Shoichi Kawamura

发明人： Masahito Takehara ,  Shoichi Kawamura

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

摘要： A nonvolatile semiconductor memory device includes a memory cell array and a control circuit configured to control reading and programming operations for reading data from and inputting data to the memory cell array, respectively. The control circuit includes first and second units. The first unit is configured to count a number of bits having logic 0 or a number of bits having logic 1, to set a logic where the counted number is greater than n/2 as an initial state to regenerate programming data, and to perform a programming operation based on the regenerated data, when simultaneously programming the programming data of n bits input for a designated address. The second unit is configured to program a recognition bit for recognizing which of the logic 0 and the logic 1 the initial state of the memory cell of the designated address is in, when the programming operation is performed.

摘要翻译： 非易失性半导体存储器件包括存储单元阵列和控制电路，该控制电路被配置为分别控制从存储单元阵列读取数据和向存储单元阵列输入数据的读取和编程操作。 控制电路包括第一和第二单元。 第一单元被配置为对具有逻辑0或具有逻辑1的位数的位数进行计数，以将计数数大于n / 2的逻辑设置为初始状态，以重新生成编程数据，并且执行 当对指定地址进行n位输入的编程数据同时编程时，基于再生数据进行编程操作。 第二单元被配置为在执行编程操作时对识别位进行编程以识别逻辑0和逻辑1中的哪一个指定地址的存储单元的初始状态。

公开(公告)号：US20100135081A1

公开(公告)日：2010-06-03

申请号：US12625723

申请日：2009-11-25

申请人： Shoichi Kawamura ,  Masahito Takehara

发明人： Shoichi Kawamura ,  Masahito Takehara

IPC分类号： G11C7/00 ,  G11C16/10 ,  G11C16/26

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

摘要： A nonvolatile semiconductor memory device includes a memory cell array and a control circuit configured to control reading and programming operations for reading data from and inputting data to the memory cell array, respectively. The control circuit includes first and second units. The first unit is configured to count a number of bits having logic 0 or a number of bits having logic 1, to set a logic where the counted number is greater than n/2 as an initial state to regenerate programming data, and to perform a programming operation based on the regenerated data, when simultaneously programming the programming data of n bits input for a designated address. The second unit is configured to program a recognition bit for recognizing which of the logic 0 and the logic 1 the initial state of the memory cell of the designated address is in, when the programming operation is performed.

摘要翻译： 非易失性半导体存储器件包括存储单元阵列和控制电路，该控制电路被配置为分别控制从存储单元阵列读取数据和向存储单元阵列输入数据的读取和编程操作。 控制电路包括第一和第二单元。 第一单元被配置为对具有逻辑0或具有逻辑1的位数的位数进行计数，以将计数数大于n / 2的逻辑设置为初始状态，以重新生成编程数据，并且执行 当对指定地址进行n位输入的编程数据同时编程时，基于再生数据进行编程操作。 第二单元被配置为在执行编程操作时对识别位进行编程以识别逻辑0和逻辑1中的哪一个指定地址的存储单元的初始状态。

公开(公告)号：US06826081B2

公开(公告)日：2004-11-30

申请号：US10638418

申请日：2003-08-12

申请人： Hirokazu Nagashima ,  Shoichi Kawamura

发明人： Hirokazu Nagashima ,  Shoichi Kawamura

IPC分类号： G11C1606

CPC分类号： G11C29/26 ,  G11C16/04

摘要： In a block which is a target of detection of flag data, a page buffer 100 reads data of memory cells 42 of each memory cell by block unit, and latches the data. A detection circuit 28 performs detection of the flag data for each block based on output of the page buffers 100 of one block.

公开(公告)号：US08605512B2

公开(公告)日：2013-12-10

申请号：US13329372

申请日：2011-12-19

申请人： Shoichi Kawamura ,  Tomohisa Miyamoto

发明人： Shoichi Kawamura ,  Tomohisa Miyamoto

IPC分类号： G11C11/40

CPC分类号： G11C16/3413 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3463 ,  G11C2216/14

摘要： A nonvolatile memory device includes a memory cell array including a plurality of bitlines, a plurality of wordlines, and a plurality of memory cells. The memory device further includes a plurality of page buffers coupled to the respective bitlines of the memory cell array, each page buffer including a latch configured to store data to be written into and read from a memory cell coupled to a respective bitline of the memory cell array. The memory device further includes a control circuit configured to execute an over-program verify operation which includes detecting an over-programmed memory cell among the plurality of memory cells with reference to pass/fail data stored in the respective latches of the plurality of page buffers, and decreasing a threshold voltage of a detected over-programmed memory cell while maintaining a threshold voltage of memory cells which have not been detected as being over-programmed.

摘要翻译： 非易失性存储器件包括包括多个位线，多个字线和多个存储器单元的存储单元阵列。 存储器装置还包括耦合到存储器单元阵列的相应位线的多个页缓冲器，每个页缓冲器包括锁存器，其被配置为存储要写入到耦合到存储器单元的相应位线的存储器单元中并从其读取的数据 数组。 该存储装置还包括控制电路，该控制电路被配置为执行过程编程验证操作，该操作包括参考存储在多个页缓冲器的相应锁存器中的通过/失败数据来检测多个存储器单元中的过度编程的存储器单元 并且在保持未被检测为过度编程的存储器单元的阈值电压的同时降低检测到的过度编程的存储单元的阈值电压。

公开(公告)号：US08264891B2

公开(公告)日：2012-09-11

申请号：US12535903

申请日：2009-08-05

申请人： Shoichi Kawamura

发明人： Shoichi Kawamura

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/344 ,  G11C16/14 ,  G11C16/16

摘要： An erase method for a non-volatile memory device having a defined erase unit divided into first and second inner erase units includes; applying an erase voltage to at least one of the first and second inner erase units in accordance with respective states of corresponding first and second fail flags, after applying the erase voltage to the at least one of the first and second inner erase units, performing an erase verification on the at least one of the first and second inner erase units, and updating the at least one of the first and second fail flags in accordance with erase verification results.

摘要翻译： 具有划分为第一和第二内部擦除单元的限定的擦除单元的非易失性存储器件的擦除方法包括： 在将擦除电压施加到第一和第二内部擦除单元中的至少一个之后，根据相应的第一和第二故障标志的相应状态，向第一和第二内部擦除单元中的至少一个施加擦除电压， 在第一和第二内部擦除单元中的至少一个擦除验证，以及根据擦除验证结果更新第一和第二失败标志中的至少一个。