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    Multi-bit ROM cell, for storing one of n>4 possible states and having bi-directional read, an array of such cells, and a method for making the array
    1.
    发明申请
    Multi-bit ROM cell, for storing one of n>4 possible states and having bi-directional read, an array of such cells, and a method for making the array 有权
    用于存储n> 4个可能状态之一并且具有双向读取的多位ROM单元，这样的单元的阵列，以及用于制作阵列的方法

    公开(公告)号：US20050231993A1

    公开(公告)日：2005-10-20

    申请号：US11157318

    申请日：2005-06-20

    申请人： Bomy Chen ,  Kai Yue ,  Dana Lee ,  Feng Gao

    发明人： Bomy Chen ,  Kai Yue ,  Dana Lee ,  Feng Gao

    IPC分类号： G11C11/56 ,  G11C17/00 ,  G11C17/12 ,  H01L21/8236 ,  H01L21/8246 ,  H01L27/112

    CPC分类号： H01L27/112 ,  G11C11/5692 ,  G11C17/12 ,  H01L27/1126 ,  H01L27/11266

    摘要： A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together. ROM cells in the same column have the first regions connected in a common first column, and second regions connected in common second column. Finally, ROM cells in adjacent columns to one side share a common first column, and cells in adjacent columns to another side share a common second column.

    摘要翻译： 多位只读存储器（ROM）单元的阵列位于具有第一浓度的第一导电类型的半导体衬底中。 每个ROM单元具有在基板中彼此间隔开的第二导电类型的第一和第二区域。 通道在第一和第二区域之间。 通道具有三个部分，第一部分，第二部分和第三部分。 门间隔开并与通道的至少第二部分绝缘。 每个ROM单元具有多个N个可能状态中的一个，其中N大于2.每个ROM单元的状态由存在或不存在在通道的第一部分中形成并与通道的第一部分相邻 第一区域和/或与第二区域相邻的通道的第三部分。 在集成电路器件的其他部分的MOS晶体管中形成扩展或光晕的同时形成这些扩展和光晕，从而降低成本。 ROM单元的阵列被布置成多个行和列，其中同一行中的ROM单元的门连接在一起。 同一列中的ROM单元具有连接在公共第一列中的第一区域和连接在公共第二列中的第二区域。 最后，一侧的相邻列中的ROM单元共享一个共同的第一列，另一侧的相邻列中的单元格共享第二列。

    Multi-bit ROM cell, for storing one of N>4 possible states and having bi-directional read, an array of such cells, and a method for making the array
    2.
    发明申请
    Multi-bit ROM cell, for storing one of N>4 possible states and having bi-directional read, an array of such cells, and a method for making the array 有权
    用于存储N> 4个可能状态之一并且具有双向读取的多位ROM单元，这样的单元的阵列，以及用于制作阵列的方法

    公开(公告)号：US20050036351A1

    公开(公告)日：2005-02-17

    申请号：US10642079

    申请日：2003-08-14

    申请人： Bomy Chen ,  Kai Yue ,  Dana Lee ,  Feng Gao

    发明人： Bomy Chen ,  Kai Yue ,  Dana Lee ,  Feng Gao

    IPC分类号： G11C11/56 ,  G11C17/00 ,  G11C17/12 ,  H01L21/8236 ,  H01L21/8246 ,  H01L27/112

    CPC分类号： H01L27/112 ,  G11C11/5692 ,  G11C17/12 ,  H01L27/1126 ,  H01L27/11266

    摘要： A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together. ROM cells in the same column have the first regions connected in a common first column, and second regions connected in common second column. Finally, ROM cells in adjacent columns to one side share a common first column, and cells in adjacent columns to another side share a common second column.

    摘要翻译： 多位只读存储器（ROM）单元的阵列位于具有第一浓度的第一导电类型的半导体衬底中。 每个ROM单元具有在基板中彼此间隔开的第二导电类型的第一和第二区域。 通道在第一和第二区域之间。 通道具有三个部分，第一部分，第二部分和第三部分。 门间隔开并与通道的至少第二部分绝缘。 每个ROM单元具有多个N个可能状态中的一个，其中N大于2.每个ROM单元的状态由存在或不存在在通道的第一部分中形成并与通道的第一部分相邻 第一区域和/或与第二区域相邻的通道的第三部分。 在集成电路器件的其他部分的MOS晶体管中形成扩展或光晕的同时形成这些扩展和光晕，从而降低成本。 ROM单元的阵列被布置成多个行和列，其中同一行中的ROM单元的门连接在一起。 同一列中的ROM单元具有连接在公共第一列中的第一区域和连接在公共第二列中的第二区域。 最后，一侧的相邻列中的ROM单元共享一个共同的第一列，另一侧的相邻列中的单元格共享第二列。

    Multi-bit ROM cell, for storing on of N>4 possible states and having bi-directional read, an array of such cells
    3.
    发明授权
    Multi-bit ROM cell, for storing on of N>4 possible states and having bi-directional read, an array of such cells 有权
    用于存储N> 4个可能状态并具有双向读取的多位ROM单元，这样的单元阵列

    公开(公告)号：US06927993B2

    公开(公告)日：2005-08-09

    申请号：US10642079

    申请日：2003-08-14

    申请人： Bomy Chen ,  Kai Man Yue ,  Dana Lee ,  Feng Gao

    发明人： Bomy Chen ,  Kai Man Yue ,  Dana Lee ,  Feng Gao

    IPC分类号： G11C11/56 ,  G11C17/00 ,  G11C17/12 ,  H01L21/8236 ,  H01L21/8246 ,  H01L27/112

    CPC分类号： H01L27/112 ,  G11C11/5692 ,  G11C17/12 ,  H01L27/1126 ,  H01L27/11266

    摘要： A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together. ROM cells in the same column have the first regions connected in a common first column, and second regions connected in common second column. Finally, ROM cells in adjacent columns to one side share a common first column, and cells in adjacent columns to another side share a common second column.

    摘要翻译： 多位只读存储器（ROM）单元的阵列位于具有第一浓度的第一导电类型的半导体衬底中。 每个ROM单元具有在基板中彼此间隔开的第二导电类型的第一和第二区域。 通道在第一和第二区域之间。 通道具有三个部分，第一部分，第二部分和第三部分。 栅极间隔开并且至少与通道的第二部分绝缘。 每个ROM单元具有多个N个可能状态中的一个，其中N大于2.每个ROM单元的状态由存在或不存在在通道的第一部分中形成并与通道的第一部分相邻 第一区域和/或与第二区域相邻的通道的第三部分。 在集成电路器件的其他部分的MOS晶体管中形成扩展或光晕的同时形成这些扩展和光晕，从而降低成本。 ROM单元的阵列被布置成多个行和列，其中同一行中的ROM单元的门连接在一起。 同一列中的ROM单元具有连接在公共第一列中的第一区域和连接在公共第二列中的第二区域。 最后，一侧的相邻列中的ROM单元共享一个共同的第一列，另一侧的相邻列中的单元格共享第二列。

    Multi-bit ROM cell, for storing one of n>4 possible states and having bi-directional read, an array of such cells, and a method for making the array
    4.
    发明授权
    Multi-bit ROM cell, for storing one of n>4 possible states and having bi-directional read, an array of such cells, and a method for making the array 有权
    用于存储n> 4个可能状态之一并且具有双向读取的多位ROM单元，这种单元的阵列，以及用于制作阵列的方法

    公开(公告)号：US06992909B2

    公开(公告)日：2006-01-31

    申请号：US11157318

    申请日：2005-06-20

    申请人： Bomy Chen ,  Kai Man Yue ,  Dana Lee ,  Feng Gao

    发明人： Bomy Chen ,  Kai Man Yue ,  Dana Lee ,  Feng Gao

    IPC分类号： G11C17/00

    CPC分类号： H01L27/112 ,  G11C11/5692 ,  G11C17/12 ,  H01L27/1126 ,  H01L27/11266

    摘要： A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together. ROM cells in the same column have the first regions connected in a common first column, and second regions connected in common second column. Finally, ROM cells in adjacent columns to one side share a common first column, and cells in adjacent columns to another side share a common second column.

    摘要翻译： 多位只读存储器（ROM）单元的阵列位于具有第一浓度的第一导电类型的半导体衬底中。 每个ROM单元具有在基板中彼此间隔开的第二导电类型的第一和第二区域。 通道在第一和第二区域之间。 通道具有三个部分，第一部分，第二部分和第三部分。 门间隔开并与通道的至少第二部分绝缘。 每个ROM单元具有多个N个可能状态中的一个，其中N大于2.每个ROM单元的状态由存在或不存在在通道的第一部分中形成并与通道的第一部分相邻 第一区域和/或与第二区域相邻的通道的第三部分。 在集成电路器件的其他部分的MOS晶体管中形成扩展或光晕的同时形成这些扩展和光晕，从而降低成本。 ROM单元的阵列被布置成多个行和列，其中同一行中的ROM单元的门连接在一起。 同一列中的ROM单元具有连接在公共第一列中的第一区域和连接在公共第二列中的第二区域。 最后，一侧的相邻列中的ROM单元共享一个共同的第一列，另一侧的相邻列中的单元格共享第二列。

    Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing
    5.
    发明授权
    Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing 有权
    双向分闸门NAND闪存结构和阵列，编程方法，擦除和读取方法以及制造方法

    公开(公告)号：US07544569B2

    公开(公告)日：2009-06-09

    申请号：US11516431

    申请日：2006-09-05

    申请人： Feng Gao ,  Ya-Fen Lin ,  John W. Cooksey ,  Changyuan Chen ,  Yuniarto Widjaja ,  Dana Lee

    发明人： Feng Gao ,  Ya-Fen Lin ,  John W. Cooksey ,  Changyuan Chen ,  Yuniarto Widjaja ,  Dana Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/42336 ,  G11C16/0425 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42328

    摘要： A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.

    摘要翻译： 在第一导电类型的半导体衬底上形成分离栅极NAND闪速存储器结构。 NAND结构包括第二导电类型的第一区域和第二导电类型的第二区域，与第一区域间隔开，由此在其间限定沟道区域。 多个浮动栅极彼此间隔开并且各自与沟道区域绝缘。 多个控制栅极彼此间隔开，每个控制栅极与沟道区域绝缘。 每个控制栅极位于一对浮动栅极之间，并且电容耦合到该对浮置栅极。 多个选择栅极彼此间隔开，每个选择栅极与沟道区域绝缘。 每个选择门位于一对浮动门之间。

    Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing
    9.
    发明授权
    Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing 有权
    双向分闸门NAND闪存结构和阵列，编程方法，擦除和读取方法以及制造方法

    公开(公告)号：US07247907B2

    公开(公告)日：2007-07-24

    申请号：US11134557

    申请日：2005-05-20

    申请人： Feng Gao ,  Ya-Fen Lin ,  John W. Cooksey ,  Changyuan Chen ,  Yuniarto Widjaja ,  Dana Lee

    发明人： Feng Gao ,  Ya-Fen Lin ,  John W. Cooksey ,  Changyuan Chen ,  Yuniarto Widjaja ,  Dana Lee

    IPC分类号： H01L29/788

    CPC分类号： H01L29/42336 ,  G11C16/0425 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42328

    摘要： A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.

    摘要翻译： 在第一导电类型的半导体衬底上形成分离栅极NAND闪速存储器结构。 NAND结构包括第二导电类型的第一区域和第二导电类型的第二区域，与第一区域间隔开，由此在其间限定沟道区域。 多个浮动栅极彼此间隔开并且各自与沟道区域绝缘。 多个控制栅极彼此间隔开，每个控制栅极与沟道区域绝缘。 每个控制栅极位于一对浮动栅极之间，并且电容耦合到该对浮置栅极。 多个选择栅极彼此间隔开，每个选择栅极与沟道区域绝缘。 每个选择门位于一对浮动门之间。