公开(公告)号：US06535031B1

公开(公告)日：2003-03-18

申请号：US10146438

申请日：2002-05-13

申请人： Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim ,  Chiakang Sung ,  Richard G Cliff ,  Joseph Huang ,  Bonnie I Wang ,  Wayne Yeung

发明人： Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim ,  Chiakang Sung ,  Richard G Cliff ,  Joseph Huang ,  Bonnie I Wang ,  Wayne Yeung

IPC分类号： H03K522

CPC分类号： H03K19/17744 ,  H03K19/018521 ,  H03K19/1778 ,  H03K19/17784

摘要： A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

公开(公告)号：US07109765B1

公开(公告)日：2006-09-19

申请号：US10996186

申请日：2004-11-22

申请人： Bonnie I Wang ,  Joseph Huang ,  Chiakang Sung ,  Xiaobao Wang ,  In Whan Kim ,  Wayne Yeung ,  Khai Nguyen

发明人： Bonnie I Wang ,  Joseph Huang ,  Chiakang Sung ,  Xiaobao Wang ,  In Whan Kim ,  Wayne Yeung ,  Khai Nguyen

IPC分类号： H03L7/06

CPC分类号： H03L7/0891 ,  H03K19/1774 ,  H03L7/0812 ,  H03L7/0996

摘要： A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.

公开(公告)号：US07196556B1

公开(公告)日：2007-03-27

申请号：US10350551

申请日：2003-01-22

申请人： Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim ,  Chiakang Sung ,  Richard G Cliff ,  Joseph Huang ,  Bonnie I Wang ,  Wayne Yeung

发明人： Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim ,  Chiakang Sung ,  Richard G Cliff ,  Joseph Huang ,  Bonnie I Wang ,  Wayne Yeung

IPC分类号： H03K3/00

CPC分类号： H03K3/35613 ,  H03K19/018528 ,  H04L25/0272

摘要： A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

摘要翻译： 可编程逻辑器件通过在器件上提供LVDS输入缓冲器和/或LVDS输出缓冲器来配备低电压差分信号（“LVDS”）。 对于LVDS成对使用的设备上的I / O引脚可以单独用于其他类型的信令。 尽管由于温度，制造过程不一致以及电源变化而导致变化，LVDS缓冲器也可以提供良好的性能和满足LVDS规范。

公开(公告)号：US07190755B1

公开(公告)日：2007-03-13

申请号：US10266092

申请日：2002-10-04

申请人： Chiakang Sung ,  Joseph Huang ,  Bonnie I Wang ,  Richard G Cliff

发明人： Chiakang Sung ,  Joseph Huang ,  Bonnie I Wang ,  Richard G Cliff

IPC分类号： H03D3/24

CPC分类号： H03K19/1774 ,  H03K19/177 ,  H03L7/0891 ,  H03L7/0996 ,  H03L7/183

摘要： A phase-locked loop circuit (“PLL”) is adjustable in both phase and frequency. By providing a plurality of taps on the voltage-controlled oscillator of the PLL, and providing separate multiplexers, each of which can select a different tap—one for the PLL feedback loop and one for the PLL output—one allows the user to adjust the phase of the output relative to that of the input. Similarly, by providing loadable pre-scale (divide by N), post-scale (divide by K) and feedback-scale (divide by M) counters, one allows the user to adjust the frequency of the output to be M/(NK) times that of the input.

摘要翻译： 锁相环电路（“PLL”）可在相位和频率两个方面调节。 通过在PLL的压控振荡器上提供多个抽头，并提供单独的多路复用器，每个复用器可以为PLL反馈回路选择不同的抽头，并为PLL输出选择一个，一个允许用户调整 输出的相位相对于输入的相位。 类似地，通过提供可加载的预缩放（除以N），后标尺（除以K）和反馈量表（除以M）计数器，允许用户将输出的频率调整为M /（NK ）倍的输入。

公开(公告)号：US07148722B1

公开(公告)日：2006-12-12

申请号：US10684341

申请日：2003-10-10

申请人： Richard G Cliff ,  Francis B Heile ,  Joseph Huang ,  David W Mendel ,  Bruce B Pedersen ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I Wang

发明人： Richard G Cliff ,  Francis B Heile ,  Joseph Huang ,  David W Mendel ,  Bruce B Pedersen ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I Wang

IPC分类号： H03K19/177

CPC分类号： H03K19/1774 ,  H03K19/17728 ,  H03K19/17744

摘要： A programmable logic integrated circuit device has several features which help it perform according to the PCI Special Interest Group's Peripheral Component Interface (“PCI”) signaling protocol. Some of the registers on the device are closely coupled for data input and output to data signal input/output pins of the device. The clock signal input terminals of at least these registers are also closely coupled to the clock signal input pin of the device. Programmable input delay is provided between the data signal input/output pins and the data input terminals of the above-mentioned registers to help compensate for clock signal skew on the device.

公开(公告)号：US07309906B1

公开(公告)日：2007-12-18

申请号：US11097503

申请日：2005-04-01

申请人： Jeffrey Tyhach ,  Bonnie I Wang ,  Yan Chong ,  Chiakang Sung

发明人： Jeffrey Tyhach ,  Bonnie I Wang ,  Yan Chong ,  Chiakang Sung

IPC分类号： H01L29/00 ,  H01L21/8242

CPC分类号： H01L29/94 ,  H01L27/0203

摘要： Improved decoupling capacitor designs and layout schemes are provided that generate high effective capacitance and high area efficiency at higher frequencies than that of previously known decoupling capacitor designs. The improved decoupling capacitor designs utilize transistor gates with shorter channel lengths to reduce the total parasitic resistance of the channel, thereby providing higher effective capacitance at higher frequencies. To enable higher area efficiency of this decoupling capacitor design, excess contacts are replaced with polysilicon in a grid or waffle pattern.

摘要翻译： 提供了改进的去耦电容器设计和布局方案，其在比先前已知的去耦电容器设计更高的频率下产生高有效电容和高的面积效率。 改进的去耦电容器设计利用具有较短沟道长度的晶体管栅极来减小沟道的总寄生电阻，从而在较高频率下提供更高的有效电容。 为了实现该去耦电容器设计的更高的面积效率，多余的触点被以栅格或华夫饼形式的多晶硅替代。