公开(公告)号：US06535031B1

公开(公告)日：2003-03-18

申请号：US10146438

申请日：2002-05-13

申请人： Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim ,  Chiakang Sung ,  Richard G Cliff ,  Joseph Huang ,  Bonnie I Wang ,  Wayne Yeung

发明人： Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim ,  Chiakang Sung ,  Richard G Cliff ,  Joseph Huang ,  Bonnie I Wang ,  Wayne Yeung

IPC分类号： H03K522

CPC分类号： H03K19/17744 ,  H03K19/018521 ,  H03K19/1778 ,  H03K19/17784

摘要： A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

公开(公告)号：US06384629B2

公开(公告)日：2002-05-07

申请号：US09738403

申请日：2000-12-15

申请人： Joseph Huang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Richard G. Cliff

发明人： Joseph Huang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Richard G. Cliff

IPC分类号： H01L2500

CPC分类号： H03K19/17736 ,  G01R31/318555 ,  G06F11/2273 ,  H03K19/17792

摘要： An improved interconnection between horizontal conductors and the input to logic elements. A signal regeneration circuit is provided in the path between the horizontal conductor and the logic element, thereby isolating and boosting the signal. This allows for faster switching operation. A path is provided allowing the selective routing of signals from the horizontal conductors to the vertical conductors, without passing through a logic element. Also, a path is provided to allow a horizontal conductors to be routed to any of a plurality of vertical conductors.

摘要翻译： 水平导体与逻辑元件输入之间的互连改善。 在水平导体和逻辑元件之间的路径中提供信号再生电路，从而隔离和升高信号。 这允许更快的切换操作。 提供路径，允许从水平导体到垂直导体的信号的选择性路由，而不通过逻辑元件。 而且，提供了一种路径，以允许水平导体被路由到多个垂直导体中的任何一个。

公开(公告)号：US06400598B1

公开(公告)日：2002-06-04

申请号：US09843299

申请日：2001-04-25

申请人： Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim ,  Chiakang Sung ,  Richard G. Cliff ,  Joseph Huang ,  Bonnie I. Wang ,  Wayne Yeung

发明人： Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim ,  Chiakang Sung ,  Richard G. Cliff ,  Joseph Huang ,  Bonnie I. Wang ,  Wayne Yeung

IPC分类号： G11C506

CPC分类号： H03K19/17744 ,  H03K19/018521 ,  H03K19/1778 ,  H03K19/17784

摘要： A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

摘要翻译： 可编程逻辑器件通过在器件上提供LVDS输入缓冲器和/或LVDS输出缓冲器来配备低电压差分信号（“LVDS”）。 对于LVDS成对使用的设备上的I / O引脚可以单独用于其他类型的信令。 尽管由于温度，制造过程不一致以及电源变化而导致变化，LVDS缓冲器也可以提供良好的性能和满足LVDS规范。

公开(公告)号：US06346827B1

公开(公告)日：2002-02-12

申请号：US09366937

申请日：1999-08-04

申请人： Wayne Yeung ,  Chiakang Sung ,  Myron W. Wong ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang ,  Joseph Huang ,  In Whan Kim

发明人： Wayne Yeung ,  Chiakang Sung ,  Myron W. Wong ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang ,  Joseph Huang ,  In Whan Kim

IPC分类号： H01L2500

CPC分类号： G11C5/147 ,  G11C5/066

摘要： A programmable input/output circuit for a programmable logic device input/output pin can be configured in a standard I/O mode, or in a reference voltage mode. The circuit includes a tristatable, but otherwise standard I/O buffer as well as a reference voltage clamp circuit. In reference voltage mode, the I/O circuit is tristated, and the reference voltage clamp circuit passes a reference voltage from the I/O pin to a reference voltage bus. In standard I/O mode, the I/O buffer is operational. The reference voltage clamp circuit isolates the I/O pin from the reference voltage bus and may include undervoltage and overvoltage protection to prevent disturbance of the reference voltage bus by an out-of-range I/O signal.

摘要翻译： 可编程逻辑器件输入/输出引脚的可编程输入/输出电路可以在标准I / O模式或参考电压模式下进行配置。 该电路包括可跟踪的标准I / O缓冲器以及参考电压钳位电路。 在参考电压模式下，I / O电路被三态化，参考电压钳位电路将参考电压从I / O引脚传递到参考电压总线。 在标准I / O模式下，I / O缓冲区可以运行。 参考电压钳位电路将I / O引脚与参考电压总线隔离，并可能包括欠压和过压保护，以防止参考电压总线受到超出范围I / O信号的干扰。

公开(公告)号：US08531205B1

公开(公告)日：2013-09-10

申请号：US13363108

申请日：2012-01-31

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Xiaobao Wang ,  Khai Nguyen ,  Joseph Huang

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Xiaobao Wang ,  Khai Nguyen ,  Joseph Huang

IPC分类号： H03K17/16

CPC分类号： H03K19/0005 ,  H03K19/018585 ,  H03K19/17744 ,  H03K19/17788

摘要： One embodiment relates to a programmable output buffer which includes first and second programmable variable-impedance single-ended driver circuits and first and second termination circuits. The first termination circuit is coupled to a first output pin which is driven by the first programmable variable-impedance single-ended driver circuit, and the second termination circuit is coupled to a second output pin which is driven by the second programmable variable-impedance single-ended driver circuit. The first and second termination circuits are programmable to either provide parallel termination for a differential signal or drive single-ended signals with the parallel termination turned off. Other embodiments and features are also disclosed.

摘要翻译： 一个实施例涉及可编程输出缓冲器，其包括第一和第二可编程可变阻抗单端驱动器电路以及第一和第二终端电路。 第一终端电路耦合到由第一可编程可变阻抗单端驱动电路驱动的第一输出引脚，第二终端电路耦合到由第二可编程可变阻抗单端驱动的第二输出引脚 驱动电路。 第一和第二终端电路是可编程的，以提供用于差分信号的并行终端或者并联终端关断的驱动单端信号。 还公开了其它实施例和特征。

公开(公告)号：US07358783B1

公开(公告)日：2008-04-15

申请号：US10400191

申请日：2003-03-25

申请人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Xiaobao Wang ,  In Whan Kim ,  Wayne Yeung ,  Khai Nguyen

发明人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Xiaobao Wang ,  In Whan Kim ,  Wayne Yeung ,  Khai Nguyen

IPC分类号： H03L7/095

CPC分类号： H03L7/0891 ,  H03F1/301 ,  H03H11/245 ,  H03K19/1774 ,  H03K23/665 ,  H03K2005/00045 ,  H03L7/081 ,  H03L7/089 ,  H03L7/0996 ,  H03L7/0997 ,  H03L7/18 ,  H03L7/183

摘要： A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit. In an implementation, the programmable phase shift circuitry is implemented using two programmable counters.

摘要翻译： 电路提供可编程相移特征，其中相移可由用户可编程地选择。 该电路可以并入可编程逻辑器件（PLD）或现场可编程门阵列（FPGA）中，以提供额外的可编程特性。 可编程相移电路可以在锁相环（PLL）或延迟锁定环（DLL）电路内实现。 在实现中，使用两个可编程计数器来实现可编程相移电路。

公开(公告)号：US06335636B1

公开(公告)日：2002-01-01

申请号：US09846409

申请日：2001-05-01

申请人： Wayne Yeung ,  Chiakang Sung ,  Myron W. Wong ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang ,  Joseph Huang ,  Im Whan Kim

发明人： Wayne Yeung ,  Chiakang Sung ,  Myron W. Wong ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang ,  Joseph Huang ,  Im Whan Kim

IPC分类号： H01L2500

CPC分类号： G11C5/147 ,  G11C5/066

摘要： A programmable input/output circuit for a programmable logic device input/output pin can be configured in a standard I/O mode, or in a reference voltage mode. The circuit includes a tristatable, but otherwise standard I/O buffer as well as a reference voltage clamp circuit. In reference voltage mode, the I/O circuit is tristated, and the reference voltage clamp circuit passes a reference voltage from the I/O pin to a reference voltage bus. In standard I/O mode, the I/O buffer is operational. The reference voltage clamp circuit isolates the I/O pin from the reference voltage bus and may include undervoltage and overvoltage protection to prevent disturbance of the reference voltage bus by an out-of-range I/O signal.

公开(公告)号：US06236231B1

公开(公告)日：2001-05-22

申请号：US09340222

申请日：1999-06-25

申请人： Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim ,  Chiakang Sung ,  Richard G. Cliff ,  Joseph Huang ,  Bonnie I. Wang ,  Wayne Yeung

发明人： Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim ,  Chiakang Sung ,  Richard G. Cliff ,  Joseph Huang ,  Bonnie I. Wang ,  Wayne Yeung

IPC分类号： H03K19177

CPC分类号： H03K19/17744 ,  H03K19/018521 ,  H03K19/1778 ,  H03K19/17784

摘要： A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

摘要翻译： 可编程逻辑器件通过在器件上提供LVDS输入缓冲器和/或LVDS输出缓冲器来配备低电压差分信号（“LVDS”）。 对于LVDS成对使用的设备上的I / O引脚可以单独用于其他类型的信令。 尽管由于温度，制造过程不一致以及电源变化而导致变化，LVDS缓冲器也可以提供良好的性能和满足LVDS规范。

公开(公告)号：US09711189B1

公开(公告)日：2017-07-18

申请号：US13209307

申请日：2011-08-12

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Xiaobao Wang ,  Yan Chong ,  Joseph Huang ,  Khai Nguyen ,  Pradeep Nagarajan

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Xiaobao Wang ,  Yan Chong ,  Joseph Huang ,  Khai Nguyen ,  Pradeep Nagarajan

IPC分类号： G11C5/14 ,  G11C11/4074

CPC分类号： G11C5/147 ,  G11C11/4074 ,  G11C19/00 ,  G11C29/021 ,  G11C29/028

摘要： A buffer circuit with an adjustable reference voltage is presented. The buffer circuit with adjustable reference voltage has an input buffer circuit that is connected to a data input and a reference voltage. The output of the input buffer circuit is connected an eye monitor circuit that generates a transition signal based on a number of transitions of an output of the input buffer circuit. The output from the eye monitor circuit is that processed by a calibration control circuit that transmits a selection signal to a multiplexer. The multiplexer selects a level of the reference voltage based on the selection signal from the calibration control circuit.

公开(公告)号：US07109765B1

公开(公告)日：2006-09-19

申请号：US10996186

申请日：2004-11-22

申请人： Bonnie I Wang ,  Joseph Huang ,  Chiakang Sung ,  Xiaobao Wang ,  In Whan Kim ,  Wayne Yeung ,  Khai Nguyen

发明人： Bonnie I Wang ,  Joseph Huang ,  Chiakang Sung ,  Xiaobao Wang ,  In Whan Kim ,  Wayne Yeung ,  Khai Nguyen

IPC分类号： H03L7/06

CPC分类号： H03L7/0891 ,  H03K19/1774 ,  H03L7/0812 ,  H03L7/0996

摘要： A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.