公开(公告)号：US07205802B1

公开(公告)日：2007-04-17

申请号：US11349516

申请日：2006-02-03

申请人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Khai Nguyen ,  Henry Kim

发明人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Khai Nguyen ,  Henry Kim

IPC分类号： H03L7/06

CPC分类号： H03K5/135 ,  H03K5/1252 ,  H03L7/0805 ,  H03L7/0814

摘要： A method and apparatus for updating the control signal received by a delay chain in a DDR application. A register is used to regulate the control signal to the delay chain. The register only updates the signal at the delay chain when a signal is not passing through the delay chain. Additionally, the present invention is directed to a delay circuit that uses a plurality of PMOS and NMOS transistors connected in parallel to each other and to an inverter that provides the desired delay. The delay provided is achieved by sequentially turning off/on a series of the NMOS/PMOS transistor pairs.

摘要翻译： 一种用于在DDR应用中更新由延迟链接收的控制信号的方法和装置。 寄存器用于调节到延迟链的控制信号。 当信号没有通过延迟链时，寄存器仅更新延迟链上的信号。 此外，本发明涉及一种延迟电路，其使用彼此并联连接的多个PMOS和NMOS晶体管以及提供所需延迟的反相器。 提供的延迟是通过顺序关闭/接通一系列NMOS / PMOS晶体管对来实现的。

公开(公告)号：US07030675B1

公开(公告)日：2006-04-18

申请号：US10932642

申请日：2004-08-31

申请人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Khai Nguyen ,  Henry Kim

发明人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Khai Nguyen ,  Henry Kim

IPC分类号： H03H11/26

CPC分类号： H03K5/135 ,  H03K5/1252 ,  H03L7/0805 ,  H03L7/0814

摘要： A method and apparatus for updating the control signal received by a delay chain in a DDR application. A register is used to regulate the control signal to the delay chain. The register only updates the signal at the delay chain when a signal is not passing through the delay chain. Additionally, the present invention is directed to a delay circuit that uses a plurality of PMOS and NMOS transistors connected in parallel to each other and to an inverter that provides the desired delay. The delay provided is achieved by sequentially turning off/on a series of the NMOS/PMOS transistor pairs.

摘要翻译： 一种用于在DDR应用中更新由延迟链接收的控制信号的方法和装置。 寄存器用于调节到延迟链的控制信号。 当信号没有通过延迟链时，寄存器仅更新延迟链上的信号。 此外，本发明涉及一种延迟电路，其使用彼此并联连接的多个PMOS和NMOS晶体管以及提供所需延迟的反相器。 提供的延迟是通过顺序关闭/接通一系列NMOS / PMOS晶体管对来实现的。

公开(公告)号：US09711189B1

公开(公告)日：2017-07-18

申请号：US13209307

申请日：2011-08-12

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Xiaobao Wang ,  Yan Chong ,  Joseph Huang ,  Khai Nguyen ,  Pradeep Nagarajan

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Xiaobao Wang ,  Yan Chong ,  Joseph Huang ,  Khai Nguyen ,  Pradeep Nagarajan

IPC分类号： G11C5/14 ,  G11C11/4074

CPC分类号： G11C5/147 ,  G11C11/4074 ,  G11C19/00 ,  G11C29/021 ,  G11C29/028

摘要： A buffer circuit with an adjustable reference voltage is presented. The buffer circuit with adjustable reference voltage has an input buffer circuit that is connected to a data input and a reference voltage. The output of the input buffer circuit is connected an eye monitor circuit that generates a transition signal based on a number of transitions of an output of the input buffer circuit. The output from the eye monitor circuit is that processed by a calibration control circuit that transmits a selection signal to a multiplexer. The multiplexer selects a level of the reference voltage based on the selection signal from the calibration control circuit.

公开(公告)号：US06433579B1

公开(公告)日：2002-08-13

申请号：US09863143

申请日：2001-05-22

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Yan Chong ,  Philip Pan ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  In Whan Kim ,  Gopinath Rangan

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Yan Chong ,  Philip Pan ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  In Whan Kim ,  Gopinath Rangan

IPC分类号： H03K19177

CPC分类号： H03K19/17744 ,  H03K19/018521 ,  H03K19/1778 ,  H03K19/17784 ,  H03K19/17792

摘要： A programmable logic device is equipped for various differential signaling schemes by providing a differential output buffer on the device that can be configured according to the needs of the particular differential signaling schemes that may be used. The buffer includes a differential output driver, an adjustable current limiting circuit between the supply voltage and the differential output driver, and an adjustable current limiting circuit between the differential output driver and ground. By selectively adjusting the two current limiting circuits, the output impedance and current, as well as the common mode output voltage and the differential output voltage can be controlled.

摘要翻译： 通过在设备上提供可根据可能使用的特定差分信令方案的需要进行配置的差分输出缓冲器，为各种差分信令方案配备了可编程逻辑器件。 缓冲器包括差分输出驱动器，电源电压和差分输出驱动器之间的可调节限流电路，以及差分输出驱动器和地之间的可调电流限制电路。 通过选择性地调节两个限流电路，可以控制输出阻抗和电流，以及共模输出电压和差分输出电压。

公开(公告)号：US07324405B1

公开(公告)日：2008-01-29

申请号：US11368369

申请日：2006-03-03

申请人： Sanjay K. Charagulla ,  Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Yan Chong

发明人： Sanjay K. Charagulla ,  Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Yan Chong

IPC分类号： G11C8/00

CPC分类号： H03K5/135 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  H03M9/00

摘要： Circuits, methods, and apparatus for filtering signals at a high-speed data interface. One exemplary embodiment is particularly configured to filter a clock signal at the end of a data burst received by a double-data rate memory interface. A clock input port is either connected or disconnected to an input cell. When a data burst is to be received, the clock input port is connected to the input cell. When the data burst concludes, the clock input port is disconnected from the input cell. In a specific embodiment, a signal is received indicating that a data burst is about to begin and the clock input port is connected to the input cell. The signal later changes state indicating that the last data bit is being received. When the last clock edge corresponding to the last data bit is received, the clock input port is disconnected from the input cell.

摘要翻译： 用于在高速数据接口处过滤信号的电路，方法和装置。 一个示例性实施例被特别地配置为在由双数据速率存储器接口接收的数据突发结束时对时钟信号进行滤波。 时钟输入端口与输入单元连接或断开。 当接收到数据脉冲串时，时钟输入端口连接到输入单元。 当数据突发结束时，时钟输入端口与输入单元断开连接。 在具体实施例中，接收到指示数据脉冲串即将开始并且时钟输入端口连接到输入单元的信号。 该信号随后改变指示正在接收最后一个数据位的状态。 当接收到与最后一个数据位相对应的最后一个时钟沿时，时钟输入端口与输入单元断开。

公开(公告)号：US07200769B1

公开(公告)日：2007-04-03

申请号：US10037861

申请日：2002-01-02

申请人： Yan Chong ,  Chiakang Sung ,  Bonnie I. Wang ,  Joseph Huang ,  Xiaobao Wang ,  Philip Pan ,  Tzung-Chin Chang

发明人： Yan Chong ,  Chiakang Sung ,  Bonnie I. Wang ,  Joseph Huang ,  Xiaobao Wang ,  Philip Pan ,  Tzung-Chin Chang

IPC分类号： G06F1/04

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C2207/108 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/091

摘要： Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an output from the frequency divider. Also included is a phase detector configured to receive the first clock signal and an output from the first variable-delay block, and an up/down counter configured to receive an output from the phase detector. A second variable-delay block is configured to receive a second clock signal and a plurality of flip-flops are configured to receive an output from the second variable-delay block. The first variable-delay block and the second variable-delay block are configured to receive an output from the up/down counter.

摘要翻译： 用于延迟多数据速率接口的时钟信号的方法和装置。 一种装置提供一种集成电路，其包括配置成接收第一时钟信号的分频器和被配置为接收来自分频器的输出的第一可变延迟块。 还包括相位检测器，被配置为接收第一时钟信号和来自第一可变延迟块的输出，以及配置为接收来自相位检测器的输出的上/下计数器。 第二可变延迟块被配置为接收第二时钟信号，并且多个触发器被配置为从第二可变延迟块接收输出。 第一可变延迟块和第二可变延迟块被配置为从加/减计数器接收输出。

公开(公告)号：US20120146700A1

公开(公告)日：2012-06-14

申请号：US13324354

申请日：2011-12-13

申请人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

发明人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

IPC分类号： H03K5/06

CPC分类号： H03K19/017581 ,  H03K19/17744

摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

摘要翻译： 用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。 本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。 模块化架构便于引脚从一代PLD迁移到下一代。

公开(公告)号：US20080201597A1

公开(公告)日：2008-08-21

申请号：US11843123

申请日：2007-08-22

申请人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H.M. Chu

发明人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H.M. Chu

IPC分类号： G06F1/12 ,  H04L7/00

CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/222

摘要： Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

摘要翻译： 用于存储器接口的电路，方法和装置，其补偿可能由飞越路由拓扑引起的时钟信号和DQ / DQS信号之间的偏差。 通过使用相位延迟时钟信号对DQ / DQS信号进行时钟补偿，其中相位延迟已校准。 在一个示例性校准例程中，向接收设备提供时钟信号。 还提供了DQ / DQS信号，并将其接收的定时进行比较。 DQ / DQS信号的延迟逐渐改变，直到DQ / DQS信号与接收设备的时钟信号对齐。 然后在器件操作期间使用该延迟来延迟提供DQ / DQS信号的寄存器的信号。 每个DQ / DQS组可以与时钟对齐，或者组中的DQS和DQ信号可以独立地对准接收器件上的时钟。

公开(公告)号：US07167023B1

公开(公告)日：2007-01-23

申请号：US11059299

申请日：2005-02-15

申请人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

发明人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H03K19/017581 ,  H03K19/17744

摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

摘要翻译： 用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。 本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。 模块化架构便于引脚从一代PLD迁移到下一代。

公开(公告)号：US06806733B1

公开(公告)日：2004-10-19

申请号：US10038737

申请日：2002-01-02

申请人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

发明人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

IPC分类号： H03K19177

CPC分类号： H03K19/1774 ,  H03K19/17744

摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

摘要翻译： 用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。 本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。 模块化架构便于引脚从一代PLD迁移到下一代。