公开(公告)号：US20050179098A1

公开(公告)日：2005-08-18

申请号：US10780513

申请日：2004-02-17

Applicant: Bor-Wen Chan ,  Chih-Hao Wang ,  Lawrance Hsu ,  Hun-Jan Tao

Inventor： Bor-Wen Chan ,  Chih-Hao Wang ,  Lawrance Hsu ,  Hun-Jan Tao

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/94

CPC classification number: H01L29/6659 ,  H01L21/28097 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823857 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/7833

Abstract: A new method to form metal silicide gates in the fabrication of an integrated circuit device is achieved. The method comprises forming polysilicon lines overlying a substrate with a dielectric layer therebetween. A first isolation layer is formed overlying the substrate and the sidewalls of the polysilicon lines. The first isolation layer does not overlie the top surface of the polysilicon lines. The polysilicon lines are partially etched down such that the top surfaces of the polysilicon lines are below the top surface of the first isolation layer. A metal layer is deposited overlying the polysilicon lines. A thermal anneal is used to completely convert the polysilicon lines to metal silicide gates. The unreacted metal layer is removed to complete the device.

Abstract translation: 实现了在制造集成电路器件中形成金属硅化物栅极的新方法。 该方法包括在其间具有介电层的衬底上形成多晶硅线。 第一隔离层形成在衬底和多晶硅线的侧壁上。 第一隔离层不覆盖多晶硅线的顶表面。 多晶硅线被部分地向下蚀刻，使得多晶硅线的顶表面在第一隔离层的顶表面下方。 金属层沉积在多晶硅线上。 使用热退火将多晶硅线完全转换成金属硅化物栅极。 去除未反应的金属层以完成该装置。

公开(公告)号：US07067391B2

公开(公告)日：2006-06-27

申请号：US10780513

申请日：2004-02-17

Applicant: Bor-Wen Chan ,  Chih-Hao Wang ,  Lawrance Hsu ,  Hun-Jan Tao

Inventor： Bor-Wen Chan ,  Chih-Hao Wang ,  Lawrance Hsu ,  Hun-Jan Tao

IPC: H01L21/28 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/302

CPC classification number: H01L29/6659 ,  H01L21/28097 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823857 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/7833

Abstract: A new method to form metal silicide gates in the fabrication of an integrated circuit device is achieved. The method comprises forming polysilicon lines overlying a substrate with a dielectric layer therebetween. A first isolation layer is formed overlying the substrate and the sidewalls of the polysilicon lines. The first isolation layer does not overlie the top surface of the polysilicon lines. The polysilicon lines are partially etched down such that the top surfaces of the polysilicon lines are below the top surface of the first isolation layer. A metal layer is deposited overlying the polysilicon lines. A thermal anneal is used to completely convert the polysilicon lines to metal silicide gates. The unreacted metal layer is removed to complete the device.

Abstract translation: 实现了在制造集成电路器件中形成金属硅化物栅极的新方法。 该方法包括在其间具有介电层的衬底上形成多晶硅线。 第一隔离层形成在衬底和多晶硅线的侧壁上。 第一隔离层不覆盖多晶硅线的顶表面。 多晶硅线被部分地向下蚀刻，使得多晶硅线的顶表面在第一隔离层的顶表面下方。 金属层沉积在多晶硅线上。 使用热退火将多晶硅线完全转换成金属硅化物栅极。 去除未反应的金属层以完成该装置。

公开(公告)号：US07122484B2

公开(公告)日：2006-10-17

申请号：US10833558

申请日：2004-04-28

Applicant: Baw-Ching Perng ,  Yi-Chen Huang ,  Jun-Lung Huang ,  Bor-Wen Chan ,  Peng-Fu Hsu ,  Hsin-Ching Shih ,  Lawrance Hsu ,  Hun-Jan Tao

Inventor： Baw-Ching Perng ,  Yi-Chen Huang ,  Jun-Lung Huang ,  Bor-Wen Chan ,  Peng-Fu Hsu ,  Hsin-Ching Shih ,  Lawrance Hsu ,  Hun-Jan Tao

IPC: H01L21/469 ,  H01L21/44

CPC classification number: H01L21/76814 ,  C11D3/3947 ,  C11D7/50 ,  C11D11/0047 ,  G03F7/423 ,  H01L21/02063 ,  H01L21/02101 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76808

Abstract: A method for removing organic material from an opening in a low k dielectric layer and above a metal layer on a substrate is disclosed. An ozone water solution comprised of one or more additives such as hydroxylamine or an ammonium salt is applied as a spray or by immersion. A chelating agent may be added to protect the metal layer from oxidation. A diketone may be added to the ozone water solution or applied in a gas or liquid phase in a subsequent step to remove any metal oxide that forms during the ozone treatment. A supercritical fluid mixture that includes CO2 and ozone can be used to remove organic residues that are not easily stripped by one of the aforementioned liquid solutions. The removal method prevents changes in the dielectric constant and refractive index of the low k dielectric layer and cleanly removes residues which improve device performance.

Abstract translation: 公开了一种从基底上的低k电介质层和金属层上方的开口除去有机材料的方法。 将由一种或多种添加剂如羟胺或铵盐组成的臭氧水溶液作为喷雾或浸渍施用。 可以加入螯合剂以保护金属层免于氧化。 可以将二酮加入到臭氧水溶液中或在随后的步骤中以气相或液相的形式施加，以除去在臭氧处理期间形成的任何金属氧化物。 可以使用包括CO 2和臭氧的超临界流体混合物来除去不易被上述液体溶液剥离的有机残留物。 去除方法防止低k电介质层的介电常数和折射率的变化，并且清洁地去除提高器件性能的残留物。

公开(公告)号：US07241674B2

公开(公告)日：2007-07-10

申请号：US10846278

申请日：2004-05-13

Applicant: Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

Inventor： Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

IPC: H01L21/3205 ,  H01L21/336

CPC classification number: H01L29/66507 ,  H01L21/28097

Abstract: A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.

Abstract translation: 提供了在具有活性区域的基板上形成硅化栅的方法。 该方法包括在有源区和栅极的一部分上形成硅化物，留下栅极的剩余部分未被硅化; 在成形步骤之后在有源区和栅上形成屏蔽层; 在所述有源区上的所述屏蔽层的部分上形成涂层; 打开所述屏蔽层以暴露所述栅极，其中所述涂层在所述打开步骤期间保护所述屏蔽层的所述部分在所述有源区域上方; 在暴露的栅极上沉积金属层; 并退火以使金属与栅极反应，使栅极的剩余部分的至少一部分硅化。

公开(公告)号：US06764903B1

公开(公告)日：2004-07-20

申请号：US10427451

申请日：2003-04-30

Applicant: Bor-Wen Chan ,  Yuan-Hung Chiu ,  Hun-Jan Tao

Inventor： Bor-Wen Chan ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC: H01L21336

CPC classification number: H01L21/28123 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139

Abstract: A method for forming a patterned target layer from a blanket target layer employs a pair of blanket hard mask layers laminated upon the blanket target layer. A patterned third mask layer is formed thereover. The method also employs four separate etch steps. One etch step is an anisotropic etch step for forming a patterned upper lying hard mask layer from the blanket upper lying hard mask layer. The patterned upper lying hard mask layer is then isotropically etched in a second etch step to form an isotropically etched patterned upper lying hard mask layer. The method is particularly useful for forming gate electrodes of diminished linewidths and enhanced dimensional control within semiconductor products.

Abstract translation: 从覆盖目标层形成图案化目标层的方法采用层叠在覆盖目标层上的一对覆盖层硬掩模层。 在其上形成图案化的第三掩模层。 该方法还采用四个独立的蚀刻步骤。 一个蚀刻步骤是用于从橡皮布上面的硬掩模层形成图案化的上卧硬掩模层的各向异性蚀刻步骤。 然后在第二蚀刻步骤中各向同性蚀刻图案化的上卧硬掩模层，以形成各向同性蚀刻的图案化的上面的硬掩模层。 该方法对于形成半导体产品中线宽减小和尺寸控制增强的栅电极特别有用。

公开(公告)号：US08299508B2

公开(公告)日：2012-10-30

申请号：US12757517

申请日：2010-04-09

Applicant: Bor Chiuan Hsieh ,  Han-Ping Chung ,  Chih-Hsin Ko ,  Bor-Wen Chan ,  Hun-Jan Tao

Inventor： Bor Chiuan Hsieh ,  Han-Ping Chung ,  Chih-Hsin Ko ,  Bor-Wen Chan ,  Hun-Jan Tao

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor device includes a substrate having shallow trench isolation and source/drain regions located therein, a gate stack located on the substrate between the source/drain regions, a first gate spacer on the sidewall of the gate stack, and a second gate spacer on the sidewall of the first gate spacer.

Abstract translation: 半导体器件包括具有浅沟槽隔离和位于其中的源极/漏极区的衬底，位于源极/漏极区之间的衬底上的栅极堆叠，栅极堆叠的侧壁上的第一栅极间隔物和位于栅极堆叠的侧壁上的第二栅极间隔 第一栅极间隔物的侧壁。

公开(公告)号：US07354847B2

公开(公告)日：2008-04-08

申请号：US10764913

申请日：2004-01-26

Applicant: Bor-Wen Chan ,  Yi-Chun Huang ,  Baw-Ching Perng ,  Hun-Jan Tao

Inventor： Bor-Wen Chan ,  Yi-Chun Huang ,  Baw-Ching Perng ,  Hun-Jan Tao

IPC: H01L21/3205 ,  H01L27/10

CPC classification number: H01L21/28123 ,  H01L21/0271 ,  H01L21/0338 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/823437

Abstract: A process for trimming a photoresist layer during the fabrication of a gate electrode in a MOSFET is described. A bilayer stack with a top photoresist layer on a thicker organic underlayer is patternwise exposed with 193 nm or 157 nm radiation to form a feature having a width w1 in the top layer. A pattern transfer through the underlayer is performed with an anisotropic etch based on H2/N2 and SO2 chemistry. The feature formed in the bilayer stack is trimmed by 10 nm or more to a width w2 by a HBr/O2/Cl2 plasma etch. The pattern transfer through an underlying gate layer is performed with a third etch based on HBr/O2/Cl2 chemistry. The underlayer is stripped by an O2 ashing with no damage to the gate electrode. Excellent profile control of the gate electrode is achieved and a larger (w1−w2) is possible than in prior art methods.

Abstract translation: 描述了在MOSFET的栅电极制造期间修整光致抗蚀剂层的工艺。 在较厚的有机底层上具有顶部光致抗蚀剂层的双层叠层以193nm或157nm辐射图案曝光以形成顶层中具有宽度w 1 1的特征。 通过底层的图案转移通过基于H 2 N 2 N 2 N 2 SO 3和SO 2 H 2化学的各向异性蚀刻进行。 通过HBr / O 2 / Cl 2等离子体将形成在双层叠层中的特征修剪10nm以上至宽度w 2 2 <！ - SIPO

公开(公告)号：US06503848B1

公开(公告)日：2003-01-07

申请号：US09989804

申请日：2001-11-20

Applicant: Bor-Wen Chan ,  Yuan-Hung Chiu ,  Huan-Just Lin ,  Hun-Jan Tao

Inventor： Bor-Wen Chan ,  Yuan-Hung Chiu ,  Huan-Just Lin ,  Hun-Jan Tao

IPC: H01L21469

CPC classification number: H01L21/32115 ,  H01L21/31055 ,  H01L21/3127 ,  H01L21/32137

Abstract: A method is disclosed for smoothing the top surface of a layer of polysilicon which, as deposited, has a rough top surface due to the formation of polysilicon grains. A polymer, such as CxFyBrz, is deposited using chemical vapor deposition. The polymer layer has a thickness large enough so that the top surface of the polymer is at least a critical distance above the peaks of the grains on the top surface of the layer of polysilicon. The layer of polymer and part of the layer of polysilicon are then etched away using an etch back method which etches the polymer and polysilicon at the same etch rate. This results in a layer of polysilicon having a smooth top surface and the same thickness over the entire layer of polysilicon.

Abstract translation: 公开了一种用于平滑多晶硅层的顶表面的方法，由于多晶硅颗粒的形成，沉积的多晶硅层具有粗糙的顶表面。 使用化学气相沉积法沉积聚合物，如CxFyBrz。 聚合物层的厚度足够大，使得聚合物的顶表面至少在多晶硅层顶表面上的晶粒峰值之上的临界距离。 然后使用以相同蚀刻速率蚀刻聚合物和多晶硅的回蚀法蚀刻掉聚合物层和多晶硅层的一部分。 这导致一层多晶硅在整个多晶硅层上具有平滑的顶表面和相同的厚度。

公开(公告)号：US20050253204A1

公开(公告)日：2005-11-17

申请号：US10846278

申请日：2004-05-13

Applicant: Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

Inventor： Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/44 ,  H01L29/40

CPC classification number: H01L29/66507 ,  H01L21/28097

Abstract: A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.

Abstract translation: 提供了在具有活性区域的基板上形成硅化栅的方法。 该方法包括在有源区和栅极的一部分上形成硅化物，留下栅极的剩余部分未被硅化; 在成形步骤之后在有源区和栅上形成屏蔽层; 在所述有源区上的所述屏蔽层的部分上形成涂层; 打开所述屏蔽层以暴露所述栅极，其中所述涂层在所述打开步骤期间保护所述屏蔽层的所述部分在所述有源区域上方; 在暴露的栅极上沉积金属层; 并退火以使金属与栅极反应，使栅极的剩余部分的至少一部分硅化。

公开(公告)号：US20070222000A1

公开(公告)日：2007-09-27

申请号：US11756131

申请日：2007-05-31

Applicant: Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

Inventor： Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

IPC: H01L27/088

CPC classification number: H01L29/66507 ,  H01L21/28097

Abstract: A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.

Abstract translation: 提供了在具有活性区域的基板上形成硅化栅的方法。 该方法包括在有源区和栅极的一部分上形成硅化物，留下栅极的剩余部分未被硅化; 在成形步骤之后在有源区和栅上形成屏蔽层; 在所述有源区上的所述屏蔽层的部分上形成涂层; 打开所述屏蔽层以暴露所述栅极，其中所述涂层在所述打开步骤期间保护所述屏蔽层的所述部分在所述有源区域上方; 在暴露的栅极上沉积金属层; 并退火以使金属与栅极反应，使栅极的剩余部分的至少一部分硅化。