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    Method to form a metal silicide gate device
    1.
    发明申请
    Method to form a metal silicide gate device 失效
    形成金属硅化物栅极器件的方法

    公开(公告)号：US20050179098A1

    公开(公告)日：2005-08-18

    申请号：US10780513

    申请日：2004-02-17

    Applicant: Bor-Wen Chan ,  Chih-Hao Wang ,  Lawrance Hsu ,  Hun-Jan Tao

    Inventor： Bor-Wen Chan ,  Chih-Hao Wang ,  Lawrance Hsu ,  Hun-Jan Tao

    IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/94

    CPC classification number: H01L29/6659 ,  H01L21/28097 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823857 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/7833

    Abstract: A new method to form metal silicide gates in the fabrication of an integrated circuit device is achieved. The method comprises forming polysilicon lines overlying a substrate with a dielectric layer therebetween. A first isolation layer is formed overlying the substrate and the sidewalls of the polysilicon lines. The first isolation layer does not overlie the top surface of the polysilicon lines. The polysilicon lines are partially etched down such that the top surfaces of the polysilicon lines are below the top surface of the first isolation layer. A metal layer is deposited overlying the polysilicon lines. A thermal anneal is used to completely convert the polysilicon lines to metal silicide gates. The unreacted metal layer is removed to complete the device.

    Abstract translation: 实现了在制造集成电路器件中形成金属硅化物栅极的新方法。 该方法包括在其间具有介电层的衬底上形成多晶硅线。 第一隔离层形成在衬底和多晶硅线的侧壁上。 第一隔离层不覆盖多晶硅线的顶表面。 多晶硅线被部分地向下蚀刻，使得多晶硅线的顶表面在第一隔离层的顶表面下方。 金属层沉积在多晶硅线上。 使用热退火将多晶硅线完全转换成金属硅化物栅极。 去除未反应的金属层以完成该装置。

    Method to form a metal silicide gate device
    2.
    发明授权
    Method to form a metal silicide gate device 失效
    形成金属硅化物栅极器件的方法

    公开(公告)号：US07067391B2

    公开(公告)日：2006-06-27

    申请号：US10780513

    申请日：2004-02-17

    Applicant: Bor-Wen Chan ,  Chih-Hao Wang ,  Lawrance Hsu ,  Hun-Jan Tao

    Inventor： Bor-Wen Chan ,  Chih-Hao Wang ,  Lawrance Hsu ,  Hun-Jan Tao

    IPC: H01L21/28 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/302

    CPC classification number: H01L29/6659 ,  H01L21/28097 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823857 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/7833

    Abstract: A new method to form metal silicide gates in the fabrication of an integrated circuit device is achieved. The method comprises forming polysilicon lines overlying a substrate with a dielectric layer therebetween. A first isolation layer is formed overlying the substrate and the sidewalls of the polysilicon lines. The first isolation layer does not overlie the top surface of the polysilicon lines. The polysilicon lines are partially etched down such that the top surfaces of the polysilicon lines are below the top surface of the first isolation layer. A metal layer is deposited overlying the polysilicon lines. A thermal anneal is used to completely convert the polysilicon lines to metal silicide gates. The unreacted metal layer is removed to complete the device.

    Abstract translation: 实现了在制造集成电路器件中形成金属硅化物栅极的新方法。 该方法包括在其间具有介电层的衬底上形成多晶硅线。 第一隔离层形成在衬底和多晶硅线的侧壁上。 第一隔离层不覆盖多晶硅线的顶表面。 多晶硅线被部分地向下蚀刻，使得多晶硅线的顶表面在第一隔离层的顶表面下方。 金属层沉积在多晶硅线上。 使用热退火将多晶硅线完全转换成金属硅化物栅极。 去除未反应的金属层以完成该装置。

    Process for removing organic materials during formation of a metal interconnect
    3.
    发明授权
    Process for removing organic materials during formation of a metal interconnect 有权
    在形成金属互连件期间去除有机材料的方法

    公开(公告)号：US07122484B2

    公开(公告)日：2006-10-17

    申请号：US10833558

    申请日：2004-04-28

    Applicant: Baw-Ching Perng ,  Yi-Chen Huang ,  Jun-Lung Huang ,  Bor-Wen Chan ,  Peng-Fu Hsu ,  Hsin-Ching Shih ,  Lawrance Hsu ,  Hun-Jan Tao

    Inventor： Baw-Ching Perng ,  Yi-Chen Huang ,  Jun-Lung Huang ,  Bor-Wen Chan ,  Peng-Fu Hsu ,  Hsin-Ching Shih ,  Lawrance Hsu ,  Hun-Jan Tao

    IPC: H01L21/469 ,  H01L21/44

    CPC classification number: H01L21/76814 ,  C11D3/3947 ,  C11D7/50 ,  C11D11/0047 ,  G03F7/423 ,  H01L21/02063 ,  H01L21/02101 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76808

    Abstract: A method for removing organic material from an opening in a low k dielectric layer and above a metal layer on a substrate is disclosed. An ozone water solution comprised of one or more additives such as hydroxylamine or an ammonium salt is applied as a spray or by immersion. A chelating agent may be added to protect the metal layer from oxidation. A diketone may be added to the ozone water solution or applied in a gas or liquid phase in a subsequent step to remove any metal oxide that forms during the ozone treatment. A supercritical fluid mixture that includes CO2 and ozone can be used to remove organic residues that are not easily stripped by one of the aforementioned liquid solutions. The removal method prevents changes in the dielectric constant and refractive index of the low k dielectric layer and cleanly removes residues which improve device performance.

    Abstract translation: 公开了一种从基底上的低k电介质层和金属层上方的开口除去有机材料的方法。 将由一种或多种添加剂如羟胺或铵盐组成的臭氧水溶液作为喷雾或浸渍施用。 可以加入螯合剂以保护金属层免于氧化。 可以将二酮加入到臭氧水溶液中或在随后的步骤中以气相或液相的形式施加，以除去在臭氧处理期间形成的任何金属氧化物。 可以使用包括CO 2和臭氧的超临界流体混合物来除去不易被上述液体溶液剥离的有机残留物。 去除方法防止低k电介质层的介电常数和折射率的变化，并且清洁地去除提高器件性能的残留物。

    Method of forming silicided gate structure
    4.
    发明授权
    Method of forming silicided gate structure 有权
    形成硅化栅结构的方法

    公开(公告)号：US07241674B2

    公开(公告)日：2007-07-10

    申请号：US10846278

    申请日：2004-05-13

    Applicant: Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

    Inventor： Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

    IPC: H01L21/3205 ,  H01L21/336

    CPC classification number: H01L29/66507 ,  H01L21/28097

    Abstract: A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.

    Abstract translation: 提供了在具有活性区域的基板上形成硅化栅的方法。 该方法包括在有源区和栅极的一部分上形成硅化物，留下栅极的剩余部分未被硅化; 在成形步骤之后在有源区和栅上形成屏蔽层; 在所述有源区上的所述屏蔽层的部分上形成涂层; 打开所述屏蔽层以暴露所述栅极，其中所述涂层在所述打开步骤期间保护所述屏蔽层的所述部分在所述有源区域上方; 在暴露的栅极上沉积金属层; 并退火以使金属与栅极反应，使栅极的剩余部分的至少一部分硅化。

    Dual hard mask layer patterning method
    5.
    发明授权
    Dual hard mask layer patterning method 失效
    双硬掩模层图案化方法

    公开(公告)号：US06764903B1

    公开(公告)日：2004-07-20

    申请号：US10427451

    申请日：2003-04-30

    Applicant: Bor-Wen Chan ,  Yuan-Hung Chiu ,  Hun-Jan Tao

    Inventor： Bor-Wen Chan ,  Yuan-Hung Chiu ,  Hun-Jan Tao

    IPC: H01L21336

    CPC classification number: H01L21/28123 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139

    Abstract: A method for forming a patterned target layer from a blanket target layer employs a pair of blanket hard mask layers laminated upon the blanket target layer. A patterned third mask layer is formed thereover. The method also employs four separate etch steps. One etch step is an anisotropic etch step for forming a patterned upper lying hard mask layer from the blanket upper lying hard mask layer. The patterned upper lying hard mask layer is then isotropically etched in a second etch step to form an isotropically etched patterned upper lying hard mask layer. The method is particularly useful for forming gate electrodes of diminished linewidths and enhanced dimensional control within semiconductor products.

    Abstract translation: 从覆盖目标层形成图案化目标层的方法采用层叠在覆盖目标层上的一对覆盖层硬掩模层。 在其上形成图案化的第三掩模层。 该方法还采用四个独立的蚀刻步骤。 一个蚀刻步骤是用于从橡皮布上面的硬掩模层形成图案化的上卧硬掩模层的各向异性蚀刻步骤。 然后在第二蚀刻步骤中各向同性蚀刻图案化的上卧硬掩模层，以形成各向同性蚀刻的图案化的上面的硬掩模层。 该方法对于形成半导体产品中线宽减小和尺寸控制增强的栅电极特别有用。

    METHOD OF FORMING SILICIDED GATE STRUCTURE
    6.
    发明申请
    METHOD OF FORMING SILICIDED GATE STRUCTURE 审中-公开
    形成硅胶结构的方法

    公开(公告)号：US20070222000A1

    公开(公告)日：2007-09-27

    申请号：US11756131

    申请日：2007-05-31

    Applicant: Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

    Inventor： Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

    IPC: H01L27/088

    CPC classification number: H01L29/66507 ,  H01L21/28097

    Abstract: A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.

    Abstract translation: 提供了在具有活性区域的基板上形成硅化栅的方法。 该方法包括在有源区和栅极的一部分上形成硅化物，留下栅极的剩余部分未被硅化; 在成形步骤之后在有源区和栅上形成屏蔽层; 在所述有源区上的所述屏蔽层的部分上形成涂层; 打开所述屏蔽层以暴露所述栅极，其中所述涂层在所述打开步骤期间保护所述屏蔽层的所述部分在所述有源区域上方; 在暴露的栅极上沉积金属层; 并退火以使金属与栅极反应，使栅极的剩余部分的至少一部分硅化。

    Method of forming a stacked capacitor structure with increased surface area for a DRAM device
    8.
    发明授权
    Method of forming a stacked capacitor structure with increased surface area for a DRAM device 有权
    形成用于DRAM器件的具有增加的表面积的堆叠电容器结构的方法

    公开(公告)号：US06706591B1

    公开(公告)日：2004-03-16

    申请号：US10054561

    申请日：2002-01-22

    Applicant: Bor-Wen Chan ,  Huan-Just Lin ,  Hun-Jan Tao

    Inventor： Bor-Wen Chan ,  Huan-Just Lin ,  Hun-Jan Tao

    IPC: H01L218242

    CPC classification number: H01L28/88 ,  H01L27/10814 ,  H01L27/10852

    Abstract: A process for forming a DRAM stacked capacitor structure with increased surface area, has been developed. The process features forming lateral grooves in the sides of a polysilicon storage node structure, during a dry etching procedure used to define the storage node structure. The grooves are selectively, and laterally formed in ion implanted veins, which in turn had been placed at various depths in an intrinsic polysilicon layer via a series of ion implantation steps, each performed at a specific implant energy. An isotopic component of the storage node structure, defining dry etch procedure, selectively etches the highly doped, ion implanted veins at a greater rate than the non-ion implanted regions of polysilicon, located between the ion implanted veins, resulting in a necked profile, storage node structure, featuring increase surface area as a result of the formation of the lateral grooves.

    Abstract translation: 已经开发了用于形成具有增加的表面积的DRAM叠层电容器结构的工艺。 该工艺在用于限定存储节点结构的干蚀刻过程中，在多晶硅存储节点结构的侧面形成横向凹槽。 这些凹槽是选择性地和侧向地形成在离子植入的静脉中，这些静脉又通过一系列离子注入步骤而被放置在本征多晶硅层中的各种深度处，每个离子注入步骤以特定的注入能量进行。 定义干法刻蚀程序的存储节点结构的同位素组分以比位于离子植入静脉之间的多晶硅的非离子注入区域更大的速率选择性地蚀刻高掺杂离子植入的静脉，导致颈缩轮廓， 存储节点结构，由于形成横向槽而具有增加的表面积。

    Multiple etch method for fabricating split gate field effect transistor (FET) device
    9.
    发明授权
    Multiple etch method for fabricating split gate field effect transistor (FET) device 有权
    用于制造分裂栅场效应晶体管（FET）器件的多次蚀刻方法

    公开(公告)号：US06656796B2

    公开(公告)日：2003-12-02

    申请号：US10047378

    申请日：2002-01-14

    Applicant: Bor-Wen Chan ,  Yu-I Wang ,  Chen-Yuan Hsu ,  Hun-Jan Tao

    Inventor： Bor-Wen Chan ,  Yu-I Wang ,  Chen-Yuan Hsu ,  Hun-Jan Tao

    IPC: H01L21336

    CPC classification number: H01L21/32139 ,  H01L21/28123 ,  H01L21/28273 ,  H01L29/42324

    Abstract: Within a method for fabricating a split gate field effect transistor (FET) device there is employed a two step etch method for forming a floating gate electrode. Within the two step etch method there is employed a patterned first masking layer and a blanket second masking layer to assist in providing the floating gate electrode with a sharply pointed tip within at least either an upper edge of the floating gate electrode or sidewall of the floating gate electrode. The sharply pointed tip provides the split gate field effect transistor (FET) device with enhanced data erasure performance.

    Abstract translation: 在用于制造分裂栅极场效应晶体管（FET）器件的方法中，采用用于形成浮置栅电极的两步蚀刻方法。 在两步蚀刻方法中，采用图案化的第一掩模层和毯状第二掩模层，以辅助浮动栅电极在浮动栅电极的上边缘或浮动栅电极的侧壁中的至少一个尖端中提供尖锐尖端 栅电极。 尖锐的尖端提供具有增强的数据擦除性能的分离栅场效应晶体管（FET）器件。

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