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    Implantable medical device incorporating adiabatic clock-powered logic
    3.
    发明授权
    Implantable medical device incorporating adiabatic clock-powered logic 失效
    可植入医疗器械，采用绝热时钟供电逻辑

    公开(公告)号：US06415181B1

    公开(公告)日：2002-07-02

    申请号：US09513045

    申请日：2000-02-25

    申请人： Carl A. Schu ,  Daniel R. Greeninger ,  David L. Thompson

    发明人： Carl A. Schu ,  Daniel R. Greeninger ,  David L. Thompson

    IPC分类号： A61N1362

    CPC分类号： A61N1/375 ,  A61N1/362 ,  A61N1/372

    摘要： Improved operating system architecture for an implantable medical device incorporating adiabatic clock-powered logic alone or in conjunction with conventional clocked logic or self-timed logic for reducing power consumption and increasing and improving processing capabilities is disclosed. The adiabatic clock-powered logic is employed to implement digital signal processors (DSPs) including analog to digital (ADC) signal converters, a state machine or the components of microprocessor cores, e.g., the CPU, arithmetic logic units (ALU), on-chip RAM and ROM and data and control buses, and other logic units, e.g., additional RAM and ROM, a direct memory address (DMA) controller, a block mover/reader, a cyclic redundancy code (CRC) calculator, and certain uplink and downlink telemetry signal processing stages. The adiabatic clocked CMOS logic is incorporated into the same IC or ICs with clocked CMOS logic and provides manufacturing economies.

    摘要翻译： 公开了用于可植入医疗设备的改进的操作系统架构，其结合绝热的时钟供电逻辑或者结合传统的时钟逻辑或自定时逻辑来降低功耗并增加和改善处理能力。 采用绝热的时钟供电逻辑来实现包括模数（ADC）信号转换器，状态机或微处理器内核的组件的数字信号处理器（DSP），例如CPU，算术逻辑单元（ALU） 芯片RAM和ROM以及数据和控制总线以及其他逻辑单元，例如附加RAM和ROM，直接存储器地址（DMA）控制器，块移动器/读取器，循环冗余码（CRC）计算器，以及某些上行链路和 下行遥测信号处理阶段。 绝缘时钟CMOS逻辑器件集成在具有时钟CMOS逻辑的同一IC或IC中，并提供制造经济。

    Implantable medical device incorporating self-timed logic
    4.
    发明授权
    Implantable medical device incorporating self-timed logic 有权

    公开(公告)号：US06389315B1

    公开(公告)日：2002-05-14

    申请号：US09513044

    申请日：2000-02-25

    申请人： Carl A. Schu ,  Daniel R. Greeninger ,  David L. Thompson

    发明人： Carl A. Schu ,  Daniel R. Greeninger ,  David L. Thompson

    IPC分类号： G61N1362

    CPC分类号： A61N1/378 ,  A61N1/3627 ,  A61N1/3708

    摘要： Improved operating system architecture for an implantable medical device incorporating self-timed logic for reducing power consumption and increasing and improving processing capabilities is disclosed. The self-timed logic is employed to implement digital signal processors (DSPs) including analog to digital (ADC) signal converters, a state machine or the components of microprocessor cores, e.g., the CPU, arithmetic logic units (ALU), on-chip RAM and ROM and data and control buses, and other logic units, e.g., additional RAM and ROM, a direct memory address (DMA) controller, a block mover/reader, a cyclic redundancy code (CRC) calculator, and certain uplink and downlink telemetry signal processing stages. The self-timed CMOS logic is incorporated into the same IC or ICs with clocked CMOS logic in a manner that minimizes the size of the clock tree serving the clocked CMOS logic, allows for efficient allocation of chip real estate, and provides manufacturing economies.

    Method and apparatus for hardware/firmware trap
    6.
    发明授权
    Method and apparatus for hardware/firmware trap 有权
    硬件/固件陷阱的方法和装置

    公开(公告)号：US07313443B2

    公开(公告)日：2007-12-25

    申请号：US11077242

    申请日：2005-03-10

    申请人： Vincent E. Splett ,  Carl A. Schu ,  Mark Haerle ,  Paul J. Huelskamp

    发明人： Vincent E. Splett ,  Carl A. Schu ,  Mark Haerle ,  Paul J. Huelskamp

    IPC分类号： A61N1/36

    CPC分类号： G06F9/4812 ,  A61N1/362 ,  A61N1/37 ,  A61N1/37211 ,  A61N1/37264 ,  G06F8/60 ,  G06F9/328 ,  G06F9/4486

    摘要： The operation of an implantable medical device executing at least one set of firmware code is modified using a hardware/firmware trap at a point of execution of the set of firmware code. A patch code for directing the implantable medical device to perform a particular task is provided for execution when the trap generates an interrupt. The operation thereafter returns to the point of execution of the set of firmware code where the interrupt was generated and execution of the set of firmware code continues in a normal manner.

    摘要翻译： 执行至少一组固件代码的可植入医疗装置的操作在固件代码集合的执行点使用硬件/固件陷阱进行修改。 提供用于引导可植入医疗装置执行特定任务的补丁代码，用于当陷阱产生中断时执行。 此后的操作返回到产生中断的固件代码集合的执行点，并且固件代码集的执行以正常方式继续。

    Power dissipation reduction in medical devices using adiabatic logic
    7.
    发明授权
    Power dissipation reduction in medical devices using adiabatic logic 失效
    使用绝热逻辑的医疗设备功耗降低

    公开(公告)号：US06438422B1

    公开(公告)日：2002-08-20

    申请号：US09467288

    申请日：1999-12-20

    申请人： Carl A. Schu ,  Daniel R. Greeninger ,  David L. Thompson

    发明人： Carl A. Schu ,  Daniel R. Greeninger ,  David L. Thompson

    IPC分类号： A61N1362

    CPC分类号： G06F1/324 ,  A61N1/025 ,  A61N1/3605 ,  A61N1/362 ,  A61N1/378 ,  G06F1/3203 ,  G06F1/3296 ,  H03K19/0019 ,  Y02D10/126 ,  Y02D10/172

    摘要： A system for minimizing power dissipation within an implantable medical device through use of adiabatic logic is disclosed. The system includes a first and a second sub-circuit of the implantable medical device. An electrical connection interconnects the first and the second sub-circuits, the electrical connection including a capacitive element. Circuitry, which charges the capacitive element of the electrical connection to generate a ramp logic signal, is connected to the capacitive element. The ramp logic signal includes a frequency of less than 500 kilohertz, thereby creating a low frequency, low power system which reduces energy dissipation to the surrounding environment.

    摘要翻译： 公开了一种通过使用绝热逻辑来最小化可植入医疗装置内的功率耗散的系统。 该系统包括可植入医疗装置的第一和第二子电路。 电连接将第一和第二子电路互连，电连接包括电容元件。 将电连接的电容元件充电以产生斜坡逻辑信号的电路连接到电容元件。 斜坡逻辑信号包括小于500千赫的频率，从而产生低频，低功率系统，从而减少对周围环境的能量耗散。

    Implantable medical device incorporating performance based adjustable power supply
    9.
    发明授权
    Implantable medical device incorporating performance based adjustable power supply 有权
    可植入医疗器械，采用基于性能的可调电源

    公开(公告)号：US6141583A

    公开(公告)日：2000-10-31

    申请号：US247458

    申请日：1999-02-09

    申请人： Forrest C. M. Pape ,  Carl A. Schu

    发明人： Forrest C. M. Pape ,  Carl A. Schu

    IPC分类号： A61N1/08 ,  A61N1/378

    CPC分类号： A61N1/378 ,  A61N1/08

    摘要： A method or apparatus for conserving power in an implantable medical device (IMD) of the type having at least one IC powered by a battery wherein, in each such IC, a voltage dependent oscillator for providing oscillator output signals at an oscillation frequency dependent upon applied supply voltage to the IC is incorporated into the IC. The voltage dependent oscillator oscillates at a frequency that is characteristic of the switching speed of all logic circuitry on the IC die that can be attained with the applied supply voltage. The applied supply voltage is regulated so that the oscillation frequency is maintained at no less than a target or desired oscillation frequency or within a desired oscillation frequency range. The power supply voltage that is applied to the IC is based directly on the performance of all logic circuitry of the IC. In order to provide the comparison function, the oscillator output signals are counted, and the oscillator output signal count accumulated over a predetermined number of system clock signals is compared to a target count that is correlated to the desired oscillation frequency. The counts are compared, and the supply voltage is adjusted upward or downward or is maintained the same dependent upon whether the oscillator output signal count falls below or rises above or is equal to the target count, respectively. The supply voltage adjustment is preferably achieved employing a digitally controlled power supply by calculating a digital voltage from the comparison of the oscillator output signal count to the target count, and storing the digital voltage in a register of the power supply.

    摘要翻译： 一种用于在具有由电池供电的至少一个IC的类型的可植入医疗装置（IMD）中节省电力的方法或装置，其中在每个这样的IC中，具有电压的振荡器，用于以取决于应用的振荡频率提供振荡器输出信号 将IC的电源电压并入IC。 电压相关振荡器以可以通过施加的电源电压获得的IC芯片上所有逻辑电路的开关速度特性的频率振荡。 所施加的电源电压被调节，使得振荡频率保持在不小于目标或期望的振荡频率或在期望的振荡频率范围内。 施加到IC的电源电压基于IC的所有逻辑电路的性能。 为了提供比较功能，对振荡器输出信号进行计数，并将累积在预定数量的系统时钟信号上的振荡器输出信号计数与与期望的振荡频率相关的目标计数进行比较。 比较计数，并且电源电压被向上或向下调整或保持相同，这取决于振荡器输出信号计数是否分别低于或等于目标计数。 优选地，通过从振荡器输出信号计数与目标计数的比较计算数字电压，并将数字电压存储在电源的寄存器中，通过使用数字控制的电源来实现电源电压调节。

    Error code calculations for data stored in an implantable medical device
    10.
    发明授权
    Error code calculations for data stored in an implantable medical device 有权
    存储在可植入医疗设备中的数据的错误代码计算

    公开(公告)号：US6128528A

    公开(公告)日：2000-10-03

    申请号：US271123

    申请日：1999-03-18

    申请人： James H. Ericksen ,  Carl A. Schu ,  Vincent E. Splett ,  Paul J. Huelskamp

    发明人： James H. Ericksen ,  Carl A. Schu ,  Vincent E. Splett ,  Paul J. Huelskamp

    IPC分类号： A61N1/37 ,  A61N1/372 ,  A61N1/39 ,  A61N1/36

    CPC分类号： A61N1/37 ,  A61N1/3706 ,  A61N1/3956

    摘要： A cyclic redundancy code (CRC) and optionally a syndrome value calculation of one or more implantable medical device (IMD) data block is conducted by block mover/reader hardware of the IMD when the data block(s) are moved and/or read. In the block read operation, each data byte or word in the block mover data register is read in a first clock cycle. In the block move operation, each data byte is read in the first clock cycle in this way and then moved to a destination register in a second clock cycle. The data CRC and optionally the syndrome value accumulate in the CRC and syndrome registers as all data bytes of the data block(s) are read in the first clock cycle. When the last data byte or word of the data block(s) is sequentially read (and moved in the block move operation), the accumulated data CRC and syndrome value are either stored as the associated data CRC and optional syndrome value or are used for comparison with a previously stored data CRC and optional syndrome value associated with the data block(s) in the comparison operation to determine if the data block(s) is corrupted.

    摘要翻译： 当数据块被移动和/或读取时，循环冗余码（CRC）和可选的一个或多个可植入医疗设备（IMD）数据块的综合征值计算由IMD的块移动器/读取器硬件进行。 在块读取操作中，在第一个时钟周期中读取块移动器数据寄存器中的每个数据字节或字。 在块移动操作中，以这种方式在第一个时钟周期读取每个数据字节，然后在第二个时钟周期内移动到目标寄存器。 在第一个时钟周期中读取数据块的所有数据字节，CRC和校验子寄存器中的数据CRC和可选的校正子值累积。 当数据块的最后一个数据字节或字被顺序读取（并在块移动操作中移动）时，累积数据CRC和校正子值被存储为相关数据CRC和可选校验值，或者用于 与先前存储的数据CRC和与比较操作中的数据块相关联的可选校验值进行比较，以确定数据块是否被破坏。