公开(公告)号：US07572689B2

公开(公告)日：2009-08-11

申请号：US11937637

申请日：2007-11-09

申请人： Brian J. Greene ,  Rajesh Rengarajan

发明人： Brian J. Greene ,  Rajesh Rengarajan

IPC分类号： H01L21/337

CPC分类号： H01L21/823425 ,  H01L21/823412 ,  H01L29/6653 ,  H01L29/7843

摘要： Methods and structures for relieving stresses in stressed semiconductor liners. A stress liner that enhances performance of either an NFET or a PFET is deposited over a semiconductor to cover the NFET and PFET. A disposable layer is deposited to entirely cover the stress liner, NFET and PFET. This disposable layer is selectively recessed to expose only the single stress liner over a gate of the NFET or PFET that is not enhanced by such stress liner, and then this exposed liner is removed to expose a top of such gate. Remaining portions of the disposable layer are removed, thereby enhancing performance of either the NFET or PFET, while avoiding degradation of the NFET or PFET not enhanced by the stress liner. The single stress liner is a tensile stress liner for enhancing performance of the NFET, or it is a compressive stress liner for enhancing performance of the PFET.

摘要翻译： 在应力半导体衬垫中减轻应力的方法和结构。 增强NFET或PFET性能的应力衬垫沉积在半导体上以覆盖NFET和PFET。 沉积一次性层以完全覆盖应力衬垫NFET和PFET。 这种一次性层被选择性地凹入以仅暴露出不受这种应力衬垫增强的NFET或PFET的栅极上的单个应力衬垫，然后去除该暴露的衬垫以露出这种栅极的顶部。 去除一次性层的剩余部分，从而增强NFET或PFET的性能，同时避免NFET或PFET不受应力衬垫增强的劣化。 单应力衬垫是用于增强NFET性能的拉伸应力衬垫，或者是用于增强PFET性能的压应力衬垫。

公开(公告)号：US07883948B2

公开(公告)日：2011-02-08

申请号：US12465817

申请日：2009-05-14

申请人： Brian J. Greene ,  Rajesh Rengarajan

发明人： Brian J. Greene ,  Rajesh Rengarajan

IPC分类号： H01L21/337

CPC分类号： H01L21/823425 ,  H01L21/823412 ,  H01L29/6653 ,  H01L29/7843

摘要： Methods and structures for relieving stresses in stressed semiconductor liners. A stress liner that enhances performance of either an NFET or a PFET is deposited over a semiconductor to cover the NFET and PFET. A disposable layer is deposited to entirely cover the stress liner, NFET and PFET. This disposable layer is selectively recessed to expose only the single stress liner over a gate of the NFET or PFET that is not enhanced by such stress liner, and then this exposed liner is removed to expose a top of such gate. Remaining portions of the disposable layer are removed, thereby enhancing performance of either the NFET or PFET, while avoiding degradation of the NFET or PFET not enhanced by the stress liner. The single stress liner is a tensile stress liner for enhancing performance of the NFET, or it is a compressive stress liner for enhancing performance of the PFET.

摘要翻译： 在应力半导体衬垫中减轻应力的方法和结构。 增强NFET或PFET性能的应力衬垫沉积在半导体上以覆盖NFET和PFET。 沉积一次性层以完全覆盖应力衬垫NFET和PFET。 这种一次性层被选择性地凹入以仅暴露出不受这种应力衬垫增强的NFET或PFET的栅极上的单个应力衬垫，然后去除该暴露的衬垫以露出这种栅极的顶部。 去除一次性层的剩余部分，从而增强NFET或PFET的性能，同时避免NFET或PFET不受应力衬垫增强的劣化。 单应力衬垫是用于增强NFET性能的拉伸应力衬垫，或者是用于增强PFET性能的压应力衬垫。

公开(公告)号：US20090236640A1

公开(公告)日：2009-09-24

申请号：US12465817

申请日：2009-05-14

申请人： Brian J. Greene ,  Rajesh Rengarajan

发明人： Brian J. Greene ,  Rajesh Rengarajan

IPC分类号： H01L29/04 ,  H01L21/3205 ,  H01L27/092

CPC分类号： H01L21/823425 ,  H01L21/823412 ,  H01L29/6653 ,  H01L29/7843

摘要： Methods and structures for relieving stresses in stressed semiconductor liners. A stress liner that enhances performance of either an NFET or a PFET is deposited over a semiconductor to cover the NFET and PFET. A disposable layer is deposited to entirely cover the stress liner, NFET and PFET. This disposable layer is selectively recessed to expose only the single stress liner over a gate of the NFET or PFET that is not enhanced by such stress liner, and then this exposed liner is removed to expose a top of such gate. Remaining portions of the disposable layer are removed, thereby enhancing performance of either the NFET or PFET, while avoiding degradation of the NFET or PFET not enhanced by the stress liner. The single stress liner is a tensile stress liner for enhancing performance of the NFET, or it is a compressive stress liner for enhancing performance of the PFET.

公开(公告)号：US20090121295A1

公开(公告)日：2009-05-14

申请号：US11937637

申请日：2007-11-09

申请人： Brian J. Greene ,  Rajesh Rengarajan

发明人： Brian J. Greene ,  Rajesh Rengarajan

IPC分类号： H01L21/311 ,  H01L27/092

CPC分类号： H01L21/823425 ,  H01L21/823412 ,  H01L29/6653 ,  H01L29/7843

摘要： Methods and structures for relieving stresses in stressed semiconductor liners. A stress liner that enhances performance of either an NFET or a PFET is deposited over a semiconductor to cover the NFET and PFET. A disposable layer is deposited to entirely cover the stress liner, NFET and PFET. This disposable layer is selectively recessed to expose only the single stress liner over a gate of the NFET or PFET that is not enhanced by such stress liner, and then this exposed liner is removed to expose a top of such gate. Remaining portions of the disposable layer are removed, thereby enhancing performance of either the NFET or PFET, while avoiding degradation of the NFET or PFET not enhanced by the stress liner. The single stress liner is a tensile stress liner for enhancing performance of the NFET, or it is a compressive stress liner for enhancing performance of the PFET.

摘要翻译： 在应力半导体衬垫中减轻应力的方法和结构。 增强NFET或PFET性能的应力衬垫沉积在半导体上以覆盖NFET和PFET。 沉积一次性层以完全覆盖应力衬垫NFET和PFET。 这种一次性层被选择性地凹入以仅暴露出不受这种应力衬垫增强的NFET或PFET的栅极上的单个应力衬垫，然后去除该暴露的衬垫以露出这种栅极的顶部。 去除一次性层的剩余部分，从而增强NFET或PFET的性能，同时避免NFET或PFET不受应力衬垫增强的劣化。 单应力衬垫是用于增强NFET性能的拉伸应力衬垫，或者是用于增强PFET性能的压应力衬垫。

公开(公告)号：US20120104511A1

公开(公告)日：2012-05-03

申请号：US13349203

申请日：2012-01-12

申请人： Victor Chan ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Chun-yung Sung ,  Min Yang

发明人： Victor Chan ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Chun-yung Sung ,  Min Yang

IPC分类号： H01L27/092

CPC分类号： H01L21/76229

摘要： The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.

摘要翻译： 本发明提供了一种半导体结构，其中不同类型的器件位于混合衬底的特定晶体取向上，这增强了每种器件的性能。 在本发明的半导体结构中，采用双沟槽隔离方案，由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离，而第二深度的第二沟槽隔离区比第 第一深度用于隔离相同极性的设备。 本发明还提供一种双沟槽半导体结构，其中pFET位于（110）结晶平面上，而nFET位于（100）晶面上。 根据本发明，不同极性的器件，即nFET和pFETs是大块状器件。

公开(公告)号：US20080290379A1

公开(公告)日：2008-11-27

申请号：US12169991

申请日：2008-07-09

申请人： Victor Chan ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Chun-yung Sung ,  Min Yang

发明人： Victor Chan ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Chun-yung Sung ,  Min Yang

IPC分类号： H01L21/8234 ,  H01L29/04

CPC分类号： H01L21/76229

摘要： The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.

摘要翻译： 本发明提供了一种半导体结构，其中不同类型的器件位于混合衬底的特定晶体取向上，这增强了每种器件的性能。 在本发明的半导体结构中，采用双沟槽隔离方案，由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离，而第二深度的第二沟槽隔离区比第 第一深度用于隔离相同极性的设备。 本发明还提供一种双沟槽半导体结构，其中pFET位于（110）结晶平面上，而nFET位于（100）晶面上。 根据本发明，不同极性的器件，即nFET和pFETs是大块状器件。

公开(公告)号：US20080044966A1

公开(公告)日：2008-02-21

申请号：US11924024

申请日：2007-10-25

申请人： Victor Chan ,  Massimo Fischetti ,  John Hergenrother ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Paul Solomon ,  Chun-yung Sung ,  Min Yang

发明人： Victor Chan ,  Massimo Fischetti ,  John Hergenrother ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Paul Solomon ,  Chun-yung Sung ,  Min Yang

IPC分类号： H01L21/8234

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/78684

摘要： The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.

公开(公告)号：US6074903A

公开(公告)日：2000-06-13

申请号：US98203

申请日：1998-06-16

申请人： Rajesh Rengarajan ,  Hirofumi Inoue ,  Radhika Srinivasan ,  Jochen Beintner

发明人： Rajesh Rengarajan ,  Hirofumi Inoue ,  Radhika Srinivasan ,  Jochen Beintner

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L27/08 ,  H01L21/8238

CPC分类号： H01L21/76237

摘要： A method for forming a electrically isolated semiconductor devices in a silicon body. A trench is formed in a selected region of the body. A barrier material is deposited over sidewalls of the trench. Portions of the barrier material are removed from a first sidewall portion of the trench to expose such first sidewall portion of the trench while leaving portions of such barrier material on a second sidewall portion of the trench to form a barrier layer thereon. A dielectric material is deposited in the trench, a portion of dielectric material being deposited on the exposed first sidewall portion of the trench and another portion of such deposited dielectric material being deposited on the barrier material. The dielectric material is annealed in an oxidizing environment to densify such deposited dielectric material, the barrier layer inhibiting oxidation of the said second sidewall portion of the trench. A plurality of the semiconductor devices is formed in the silicon body with such devices being electrically isolated by the dielectric material in the trench.

摘要翻译： 一种用于在硅体中形成电绝缘的半导体器件的方法。 在身体的选定区域中形成沟槽。 阻挡材料沉积在沟槽的侧壁上。 阻挡材料的一部分从沟槽的第一侧壁部分被去除以暴露沟槽的这种第一侧壁部分，同时将这种阻挡材料的一部分留在沟槽的第二侧壁部分上以在其上形成阻挡层。 电介质材料沉积在沟槽中，介电材料的一部分沉积在暴露的沟槽的第一侧壁部分上，另一部分沉积的介电材料沉积在阻挡材料上。 电介质材料在氧化环境中退火以致密化这种淀积的介电材料，阻挡层阻止沟槽的所述第二侧壁部分的氧化。 在硅体中形成多个半导体器件，这些器件通过沟槽中的电介质材料电隔离。

公开(公告)号：US08097516B2

公开(公告)日：2012-01-17

申请号：US12169991

申请日：2008-07-09

申请人： Victor Chan ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Chun-yung Sung ,  Min Yang

发明人： Victor Chan ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Chun-yung Sung ,  Min Yang

IPC分类号： H01L21/336

CPC分类号： H01L21/76229

摘要： The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.

摘要翻译： 本发明提供了一种半导体结构，其中不同类型的器件位于混合衬底的特定晶体取向上，这增强了每种器件的性能。 在本发明的半导体结构中，采用双沟槽隔离方案，由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离，而第二深度的第二沟槽隔离区比第 第一深度用于隔离相同极性的设备。 本发明还提供一种双沟槽半导体结构，其中pFET位于（110）结晶平面上，而nFET位于（100）晶面上。 根据本发明，不同极性的器件，即nFET和pFETs是大块状器件。

公开(公告)号：US06960818B1

公开(公告)日：2005-11-01

申请号：US09000626

申请日：1997-12-30

申请人： Rajesh Rengarajan ,  Venkatachalam C. Jaiprakash

发明人： Rajesh Rengarajan ,  Venkatachalam C. Jaiprakash

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L29/00

CPC分类号： H01L27/10861 ,  H01L21/76224 ,  Y10S148/05

摘要： A method for reducing hot carrier reliability problems within an integrated circuit device. The method includes forming a shallow trench isolation structure incorporated with the device by filling a trench with a photoresist plug and removing a portion of the photoresist plug to a level below the depth of a channel also incorporated with the device. A nitride liner disposed within the trench under the photoresist plug is then recessed to a level substantially equal to the level of the photoresist material, which is then removed. The method further includes the deposition of oxide fill within the trench, thereby encapsulating the recessed nitride liner.

摘要翻译： 一种降低集成电路装置内热载体可靠性问题的方法。 该方法包括通过用光致抗蚀剂插塞填充沟槽并且将光致抗蚀剂插塞的一部分移除到还与器件结合的通道的深度的水平面下，形成并入器件的浅沟槽隔离结构。 然后将设置在光致抗蚀剂插塞下方的沟槽内的氮化物衬垫凹入到基本上等于光致抗蚀剂材料的水平的水平，然后将其除去。 该方法还包括在沟槽内沉积氧化物填充物，从而封装凹陷的氮化物衬垫。