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    Memory device and method having data path with multiple prefetch I/O configurations
    2.
    发明授权
    Memory device and method having data path with multiple prefetch I/O configurations 失效
    具有多个预取I / O配置的数据路径的存储器件和方法

    公开(公告)号：US06882579B2

    公开(公告)日：2005-04-19

    申请号：US10705388

    申请日：2003-11-10

    申请人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

    发明人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

    IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  G11C11/4096 ,  G11C7/00

    CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

    摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

    摘要翻译： 存储器件可以在高模式或低速模式下操作。 在任一模式中，来自两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器组中。 在高速模式下，预取数据位并行传输到4个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于4个数据总线 终端。 在低速模式下，两组预取数据位并行传送到8个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于8个数据中的相应一个 巴士总站。

    System latency levelization for read data
    3.
    发明授权
    System latency levelization for read data 失效
    读取数据的系统延迟级别化

    公开(公告)号：US06851016B2

    公开(公告)日：2005-02-01

    申请号：US10720183

    申请日：2003-11-25

    申请人： Jeffery W. Janzen ,  Brent Keeth ,  Kevin J. Ryan ,  Troy A. Manning ,  Brian Johnson

    发明人： Jeffery W. Janzen ,  Brent Keeth ,  Kevin J. Ryan ,  Troy A. Manning ,  Brian Johnson

    IPC分类号： G06F12/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407

    CPC分类号： G11C7/22 ,  G11C7/1072

    摘要： In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.

    摘要翻译： 在高速存储器子系统中，每个存储器件的最小器件读取延迟和存储器件与存储器控制器之间的信号传播时间差异都会导致系统读取延迟的变化。 本发明通过比较每个设备的系统读取延迟的差异，然后用设备系统读取延迟来操作每个存储器设备来均衡每个存储器设备在高速存储器系统中的系统读取延迟，这使得每个设备呈现相同的系统 读延迟。

    Multi-mode synchronous memory device and methods of operating and testing same
    8.
    发明授权
    Multi-mode synchronous memory device and methods of operating and testing same 失效

    公开(公告)号：US06842398B2

    公开(公告)日：2005-01-11

    申请号：US10703275

    申请日：2003-11-07

    申请人： Brian Johnson ,  Brent Keeth ,  Jeffrey W. Janzen ,  Troy A. Manning ,  Chris G. Martin

    发明人： Brian Johnson ,  Brent Keeth ,  Jeffrey W. Janzen ,  Troy A. Manning ,  Chris G. Martin

    IPC分类号： G01R31/28 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C29/14 ,  G11C8/00

    CPC分类号： G11C29/12015 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C29/14

    摘要： A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal. control circuitry in the device is responsive to a predetermined sequence of asynchronous signals applied to the device's asynchronous input terminals to place the device in an alternative mode of operation in which the internal clocking circuit is disabled, such that the device may be operated in the alternative mode using an external clock signal having a frequency less than the predetermined minimum frequency. The alternative mode of operation facilitates testing of the device at a speed less than the minimum frequency specified for the normal mode of operation.

    Memory device and method having data path with multiple prefetch I/O configurations
    9.
    发明授权
    Memory device and method having data path with multiple prefetch I/O configurations 有权
    具有多个预取I / O配置的数据路径的存储器件和方法

    公开(公告)号：US06693836B2

    公开(公告)日：2004-02-17

    申请号：US10278528

    申请日：2002-10-22

    申请人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

    发明人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

    IPC分类号： G11C700

    CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

    摘要： A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

    摘要翻译： 存储器件可以在高模式或低速模式下操作。 在任一模式中，来自两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器组中。 在高速模式下，预取数据位并行传输到4个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于4个数据总线 终端。 在低速模式下，两组预取数据位并行传送到8个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于8个数据中的相应一个 巴士总站。

    Memory device and method having data path with multiple prefetch I/O configurations
    10.
    发明授权
    Memory device and method having data path with multiple prefetch I/O configurations 有权
    具有多个预取I / O配置的数据路径的存储器件和方法

    公开(公告)号：US06690609B2

    公开(公告)日：2004-02-10

    申请号：US10278529

    申请日：2002-10-22

    申请人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

    发明人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

    IPC分类号： G11C700

    CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

    摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

    摘要翻译： 存储器件可以在高模式或低速模式下操作。 在任一模式中，来自两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器组中。 在高速模式下，预取数据位并行传输到4个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于4个数据总线 终端。 在低速模式下，两组预取数据位并行传送到8个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于8个数据中的相应一个 巴士总站。