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公开(公告)号：US06842398B2
公开(公告)日：2005-01-11
申请号：US10703275
申请日：2003-11-07
IPC分类号： G01R31/28 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , G11C29/14 , G11C8/00
CPC分类号： G11C29/12015 , G11C7/1078 , G11C7/109 , G11C7/22 , G11C7/222 , G11C29/14
摘要： A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal. control circuitry in the device is responsive to a predetermined sequence of asynchronous signals applied to the device's asynchronous input terminals to place the device in an alternative mode of operation in which the internal clocking circuit is disabled, such that the device may be operated in the alternative mode using an external clock signal having a frequency less than the predetermined minimum frequency. The alternative mode of operation facilitates testing of the device at a speed less than the minimum frequency specified for the normal mode of operation.
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2.发明授权Multi-mode synchronous memory device and method of operating and testing same 有权多模同步存储器件及其操作与测试方法相同公开(公告)号：US06678205B2
公开(公告)日：2004-01-13
申请号：US10036141
申请日：2001-12-26
IPC分类号： G11C800
CPC分类号： G11C29/12015 , G11C7/1078 , G11C7/109 , G11C7/22 , G11C7/222 , G11C29/14
摘要： A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal, control circuitry in the device is responsive to a predetermined sequence of asynchronous signals applied to the device's asynchronous input terminals to place the device in an alternative mode of operation in which the internal clocking circuit is disabled, such that the device may be operated in the alternative mode using an external clock signal having a frequency less than the predetermined minimum frequency. The alternative mode of operation facilitates testing of the device at a speed less than the minimum frequency specified for the normal mode of operation.
摘要翻译： 同步半导体存储器件可以在正常模式和替代模式下操作。 半导体器件具有用于接收多个同步捕获的输入信号的命令总线和用于接收多个异步输入信号的多个异步输入端子。 该装置还具有用于在其上接收外部时钟信号的时钟输入，该装置由制造商指定为使用具有不小于预定最小频率的频率的外部时钟信号在正常模式下操作。 内部延迟锁定环（DLL）时钟电路耦合到时钟输入端，并且在正常操作模式下响应于外部时钟信号响应以产生至少一个内部时钟信号，该设备中的控制电路响应于 施加到设备的异步输入终端的预定的异步信号序列，以将设备置于其中禁用内部时钟电路的替代操作模式，使得可以使用具有频率的外部时钟信号在替代模式下操作该设备 小于预定的最小频率。 替代的操作模式便于以低于为正常操作模式指定的最小频率的速度测试设备。
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3.发明授权Multi-mode synchronous memory device and methods of operating and testing same 失效多模同步存储器件及其操作和测试方法相同公开(公告)号：US07057967B2
公开(公告)日：2006-06-06
申请号：US11001231
申请日：2004-12-01
IPC分类号： G11C8/00
CPC分类号： G11C29/12015 , G11C7/1078 , G11C7/109 , G11C7/22 , G11C7/222 , G11C29/14
摘要： A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal. control circuitry in the device is responsive to a predetermined sequence of asynchronous signals applied to the device's asynchronous input terminals to place the device in an alternative mode of operation in which the internal clocking circuit is disabled, such that the device may be operated in the alternative mode using an external clock signal having a frequency less than the predetermined minimum frequency. The alternative mode of operation facilitates testing of the device at a speed less than the minimum frequency specified for the normal mode of operation.
摘要翻译： 同步半导体存储器件可以在正常模式和替代模式下操作。 半导体器件具有用于接收多个同步捕获的输入信号的命令总线和用于接收多个异步输入信号的多个异步输入端子。 该装置还具有用于在其上接收外部时钟信号的时钟输入，该装置由制造商指定为使用具有不小于预定最小频率的频率的外部时钟信号在正常模式下操作。 内部延迟锁定环（DLL）时钟电路耦合到时钟输入端并且在正常操作模式下响应于外部时钟信号响应以产生至少一个内部时钟信号。 设备中的控制电路响应于施加到设备的异步输入端子的预定的异步信号序列，以将设备置于其中内部时钟电路被禁用的替代操作模式，使得该设备可以以替代方式操作 模式使用具有小于预定最小频率的频率的外部时钟信号。 替代的操作模式便于以低于为正常操作模式指定的最小频率的速度测试设备。
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4.发明授权Method and structures for reduced parasitic capacitance in integrated circuit metallizations 有权集成电路金属化中减小寄生电容的方法和结构公开(公告)号：US07160795B2
公开(公告)日：2007-01-09
申请号：US10293789
申请日：2002-11-12
申请人： Shubneesh Batra , Michael D. Chaine , Brent Keeth , Salman Akram , Troy A. Manning , Brian Johnson , Chris G. Martin , Todd A. Merritt , Eric J. Smith
发明人： Shubneesh Batra , Michael D. Chaine , Brent Keeth , Salman Akram , Troy A. Manning , Brian Johnson , Chris G. Martin , Todd A. Merritt , Eric J. Smith
IPC分类号： H01L21/44
CPC分类号： H01L24/05 , H01L23/5222 , H01L24/03 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01061 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/30105
摘要： A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal level below the bond pad and forming an underlying metal pad on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads to the area of the bond pad is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.
摘要翻译： 描述了一种降低具有三个或更多个金属水平的集成电路中的寄生电容的方法。 该方法包括形成至少部分地暴露在集成电路的顶表面处的接合焊盘，在接合焊盘下方的金属层上形成金属焊盘，并在一个或多个下金属层的每一个上形成下面的金属焊盘。 在所示的实施例中，下面的金属焊盘中的至少一个的面积与焊盘的面积之比小于30％。 寄生电容因此大大降低，信号传播速度提高。
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5.发明授权Method and structures for reduced parasitic capacitance in integrated circuit metallizations 有权集成电路金属化中减小寄生电容的方法和结构公开(公告)号：US06909196B2
公开(公告)日：2005-06-21
申请号：US10178172
申请日：2002-06-21
申请人： Shubneesh Batra , Michael D. Chaine , Brent Keeth , Salman Akram , Troy A. Manning , Brian Johnson , Chris G. Martin , Todd A. Merritt , Eric J. Smith
发明人： Shubneesh Batra , Michael D. Chaine , Brent Keeth , Salman Akram , Troy A. Manning , Brian Johnson , Chris G. Martin , Todd A. Merritt , Eric J. Smith
IPC分类号： H01L23/485 , H01L23/522 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L23/5222 , H01L24/03 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01061 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/30105
摘要： A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal level below the bond pad and forming an underlying metal pad on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads to the area of the bond pad is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.
摘要翻译： 描述了一种降低具有三个或更多个金属水平的集成电路中的寄生电容的方法。 该方法包括形成至少部分地暴露在集成电路的顶表面处的接合焊盘，在接合焊盘下方的金属层上形成金属焊盘，并在一个或多个下金属层的每一个上形成下面的金属焊盘。 在所示的实施例中，下面的金属焊盘中的至少一个的面积与焊盘的面积之比小于30％。 寄生电容因此大大降低，信号传播速度提高。
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公开(公告)号：US20130003473A1
公开(公告)日：2013-01-03
申请号：US13616704
申请日：2012-09-14
申请人： Brent Keeth , Chris G. Martin , Troy A. Manning , Joe M. Jeddeloh , Timothy B. Cowles , Jim Rehmeyer , Paul A. LaBerge
发明人： Brent Keeth , Chris G. Martin , Troy A. Manning , Joe M. Jeddeloh , Timothy B. Cowles , Jim Rehmeyer , Paul A. LaBerge
IPC分类号： G11C7/10
CPC分类号： G06F12/08 , G06F12/10 , G11C5/025 , G11C29/04 , G11C29/18 , G11C29/76 , G11C29/78 , G11C29/808 , G11C29/812 , G11C29/883 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.
摘要翻译： 各种实施例包括具有布置在堆叠中的多个骰子的装置，系统和方法，其中有缺陷的单元可以被同一裸片上的备用单元或不同的管芯替代。 描述其他实施例。
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公开(公告)号：US06847583B2
公开(公告)日：2005-01-25
申请号：US10778145
申请日：2004-02-17
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G11C7/10 , G11C7/20 , G11C7/22 , G11C11/4072 , G11C11/409 , G11C8/00
CPC分类号： G11C7/1066 , G06F13/1689 , G06F13/4243 , G11C7/1006 , G11C7/1072 , G11C7/20 , G11C7/22 , G11C11/4072 , G11C11/409 , G11C2207/107 , G11C2207/2254 , G11C2207/2281
摘要： The read latency of a plurality of memory devices in a high speed synchronous memory subsystem is equalized through the use of at least one flag signal. The flag signal has equivalent signal propagation characteristics read clock signal, thereby automatically compensating for the effect of signal propagation. After detecting the flag signal, a memory device will begin outputting data associated with a previously received read command in a predetermined number of clock cycles. For each of the flag signal, the memory controller, at system initialization, determines the required delay between issuing a read command and issuing the flag signal to equalize the system read latencies. The delay(s) are then applied to read transactions during regular operation of the memory system.
摘要翻译： 通过使用至少一个标志信号来使高速同步存储器子系统中的多个存储器件的读取等待时间被均衡。 标志信号具有等效信号传播特性的读时钟信号，从而自动补偿信号传播的影响。 在检测到标志信号之后，存储器件将以预定数量的时钟周期开始输出与先前接收到的读取命令相关联的数据。 对于每个标志信号，存储器控制器在系统初始化时确定在发出读取命令和发出标志信号以均衡系统读取延迟之间所需的延迟。 然后将延迟应用于在存储器系统的常规操作期间读取事务。
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公开(公告)号：US06724666B2
公开(公告)日：2004-04-20
申请号：US10222798
申请日：2002-08-19
IPC分类号： G11C700
CPC分类号： G11C7/1066 , G06F13/1689 , G06F13/4243 , G11C7/1006 , G11C7/1072 , G11C7/20 , G11C7/22 , G11C11/4072 , G11C11/409 , G11C2207/107 , G11C2207/2254 , G11C2207/2281
摘要： The read latency of a plurality of memory devices in a high speed synchronous memory subsystem is equalized through the use of at least one flag signal. The flag signal has equivalent signal propagation characteristics read clock signal, thereby automatically compensating for the effect of signal propagation. After detecting the flag signal, a memory device will begin outputting data associated with a previously received read command in a predetermined number of clock cycles. For each of the flag signal, the memory controller, at system initialization, determines the required delay between issuing a read command and issuing the flag signal to equalize the system read latencies. The delay(s) are then applied to read transactions during regular operation of the memory system.
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公开(公告)号：US07835207B2
公开(公告)日：2010-11-16
申请号：US12246882
申请日：2008-10-07
申请人： Brent Keeth , Chris G. Martin , Troy A. Manning , Joe M. Jeddeloh , Timothy B. Cowles , Jim Rehmeyer , Paul A. LaBerge
发明人： Brent Keeth , Chris G. Martin , Troy A. Manning , Joe M. Jeddeloh , Timothy B. Cowles , Jim Rehmeyer , Paul A. LaBerge
CPC分类号： G06F12/08 , G06F12/10 , G11C5/025 , G11C29/04 , G11C29/18 , G11C29/76 , G11C29/78 , G11C29/808 , G11C29/812 , G11C29/883 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.
摘要翻译： 各种实施例包括具有布置在堆叠中的多个骰子的装置，系统和方法，其中有缺陷的单元可以被同一裸片上的备用单元或不同的管芯替代。
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公开(公告)号：US07492652B2
公开(公告)日：2009-02-17
申请号：US11876477
申请日：2007-10-22
申请人： Chris G. Martin , Troy A. Manning , Brent Keeth
发明人： Chris G. Martin , Troy A. Manning , Brent Keeth
IPC分类号： G11C7/00
CPC分类号： G11C17/165 , G11C29/4401 , G11C29/789 , G11C29/802 , G11C29/808 , G11C2029/4402
摘要： An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.
摘要翻译： 用于修复半导体存储器件的装置和方法包括：第一存储单元阵列，第一冗余单元阵列和修复电路，被配置为在第一存储单元阵列中非易失性地存储指定至少一个有缺陷的存储单元的第一地址。 第一易失性高速缓存存储对应于指定所述至少一个有缺陷的存储器单元的第一地址的第一高速缓存地址。 修复电路将指定第一存储单元阵列的至少一个缺陷存储单元的第一地址分配给第一易失性高速缓存。 当第一存储器访问对应于第一缓存地址时，匹配电路将来自第一冗余单元阵列的至少一个冗余存储单元替换为第一存储单元阵列中的至少一个有缺陷的存储单元。
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