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1.发明授权Method and apparatus to improve latency experienced by an agent under a round robin arbitration scheme 失效一种用于改善代理在循环仲裁方案下经历的延迟的方法和装置
公开(公告)号：US5640519A
公开(公告)日：1997-06-17
申请号：US528914
申请日：1995-09-15
IPC分类号： G06F13/364 , G06F13/36 , G06F13/362
CPC分类号： G06F13/364
摘要： An arbitration circuit which controls arbitration for a resource by a first plurality of agents including a latency sensitive agent. The arbitration circuit comprises a mapping circuit and an arbiter. The mapping circuit is coupled to the first plurality of agents in order to receive a resource request signal from the latency sensitive agent and thereafter produce a plurality of request signals identical to the resource request signal. These request signals are input into at least a first and second I/O ports of the arbiter. The arbiter, which is coupled to the mapping circuit, including a second plurality of I/O ports and a second plurality of control ports each corresponding to one of the I/O ports. The arbiter is configured to arbitrate request signals input into the second plurality of I/O ports including the plurality of request signals, to monitor which I/O port was last activated, and to deactivate a control port associated with the I/O port thereby producing a control signal. This control signal signals the mapping circuit to disable at least one of the plurality of request signals upon detecting that the control signal is associated with the first I/O port or the second I/O port.
摘要翻译： 仲裁电路，其由包括等待时间敏感代理的第一多个代理控制资源的仲裁。 仲裁电路包括映射电路和仲裁器。 映射电路耦合到第一多个代理，以便从等待时间敏感代理接收资源请求信号，然后产生与资源请求信号相同的多个请求信号。 这些请求信号被输入到仲裁器的至少第一和第二I / O端口中。 耦合到映射电路的仲裁器包括每个对应于一个I / O端口的第二多个I / O端口和第二多个控制端口。 仲裁器被配置为仲裁输入到包括多个请求信号的第二多个I / O端口的请求信号，以监视上一次激活的I / O端口，并且停用与I / O端口相关联的控制端口，从而 产生控制信号。 该控制信号在检测到控制信号与第一I / O端口或第二I / O端口相关联时，通知该映射电路来禁用多个请求信号中的至少一个。
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2.发明授权
公开(公告)号：US5603010A
公开(公告)日：1997-02-11
申请号：US580323
申请日：1995-12-28
CPC分类号： G06F13/4239
摘要： A method of improving computer system performance during memory reads. Prior art computer systems experience a considerable time penalty during microprocessor reads from system memory. This time penalty is mitigated by the method of the present invention, wherein data is speculatively retrieved from system memory upon receipt of a microprocessor read request. A microprocessor initiates a read request which is decoded by a memory controller. Before the decoding has completed, the memory controller speculatively begins to retrieve data from the system memory device. Thus if the decode step determines that the requested data is in system memory, the time required to retrieve the data is decreased.
摘要翻译： 一种在存储器读取期间提高计算机系统性能的方法。 现有技术的计算机系统在从系统存储器的微处理器读取期间经历相当多的时间损失。 通过本发明的方法减轻了该时间的损失，其中在接收到微处理器读取请求时，从系统存储器中推测性地检索数据。 微处理器启动由存储器控制器解码的读请求。 在解码完成之前，存储器控制器推测开始从系统存储器件中检索数据。 因此，如果解码步骤确定所请求的数据在系统存储器中，则检索数据所需的时间减少。
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3.发明授权Method and apparatus for automatically detecting whether a board level cache is implemented with Mcache 失效用于自动检测是否通过Mcache实现板级缓存的方法和装置公开(公告)号：US06535956B1
公开(公告)日：2003-03-18
申请号：US09198130
申请日：1998-11-23
申请人： James M. Dodd , Brian K. Langendorf
发明人： James M. Dodd , Brian K. Langendorf
IPC分类号： G06F1200
CPC分类号： G06F12/0802
摘要： A mechanism for automatically detecting whether a selected type of cache memory is implemented within a cache memory element. The mechanism features a dedicated control line coupled between the cache memory element and a system controller. Logic circuitry is coupled to the control line to force the line to a first logic level in the event that the cache memory element has no connection to support the control line. However, if the cache memory element contains the selected type of cache memory, the logic circuitry is unable to for force the control line to go from a second logic level to the first logic level. After system reset, the system controller samples the voltage on the control line to determine whether the cache memory element is implemented with the selected type of cache memory.
摘要翻译： 用于自动检测在高速缓冲存储器元件内是否实现所选类型的高速缓冲存储器的机构。 该机制具有耦合在高速缓冲存储器元件和系统控制器之间的专用控制线。 在高速缓冲存储器元件没有连接以支持控制线的情况下，逻辑电路耦合到控制线以强制线路进入第一逻辑电平。 然而，如果高速缓冲存储器元件包含所选择的高速缓冲存储器类型，则逻辑电路不能强制控制线从第二逻辑电平转到第一逻辑电平。 系统复位后，系统控制器对控制线上的电压进行采样，以确定高速缓存存储器元件是否使用选定类型的高速缓冲存储器实现。
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4.发明授权
公开(公告)号：US5898856A
公开(公告)日：1999-04-27
申请号：US528699
申请日：1995-09-15
申请人： James M. Dodd , Brian K. Langendorf
发明人： James M. Dodd , Brian K. Langendorf
CPC分类号： G06F12/0802
摘要： A mechanism for automatically detecting whether a selected type of cache memory is implemented within a cache memory element. The mechanism features a dedicated control line coupled between the cache memory element and a system controller. Logic circuitry is coupled to the control line to force the line to a first logic level in the event that the cache memory element has no connection to support the control line. However, if the cache memory element contains the selected type of cache memory, the logic circuitry is unable to for force the control line to go from a second logic level to the first logic level. After system reset, the system controller samples the voltage on the control line to determine whether the cache memory element is implemented with the selected type of cache memory.
摘要翻译： 用于自动检测在高速缓冲存储器元件内是否实现所选类型的高速缓冲存储器的机构。 该机制具有耦合在高速缓冲存储器元件和系统控制器之间的专用控制线。 在高速缓冲存储器元件没有连接以支持控制线的情况下，逻辑电路耦合到控制线以强制线路进入第一逻辑电平。 然而，如果高速缓冲存储器元件包含所选择的高速缓冲存储器类型，则逻辑电路不能强制控制线从第二逻辑电平转到第一逻辑电平。 系统复位后，系统控制器对控制线上的电压进行采样，以确定高速缓存存储器元件是否使用选定类型的高速缓冲存储器实现。
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5.发明授权Method and apparatus for controlling of a memory subsystem installed with standard page mode memory and an extended data out memory 失效用于控制安装有标准页面模式存储器和扩展数据输出存储器的存储器子系统的方法和装置公开(公告)号：US06725349B2
公开(公告)日：2004-04-20
申请号：US10389092
申请日：2003-03-13
IPC分类号： G06F1200
CPC分类号： G11C7/1024 , G11C7/1021 , G11C11/4076 , G11C11/4082
摘要： A method and apparatus for optimizing control on a bank to bank basis of a memory subsystem having a plurality of memory banks which are installed with different types of dynamic random access memory (DRAM) devices is presented. The present invention includes an improved DRAM controller comprises a set of configuration registers which store configuration bits corresponding to each memory bank in the main memory that is populated with the DRAM devices. The memory controller also includes a detection logic which together with a memory bank decode logic enables the memory controller determine whether a particular memory bank is populated with a page mode DRAM or an extended data out DRAM. The preferred embodiment also includes a column address strobe state machine which automatically controls timing requirements of both type of DRAM devices installed in the main memory to quickly and efficiently handle access requests.
摘要翻译： 提出一种用于优化具有多个存储器组的存储器子系统的基于存储体的控制的方法和装置，所述多个存储器组安装有不同类型的动态随机存取存储器（DRAM）设备。 本发明包括一种改进的DRAM控制器，其包括一组配置寄存器，其存储与主存储器中与DRAM装置填充的每个存储体相对应的配置位。 存储器控制器还包括检测逻辑，其与存储体解码逻辑一起使能存储器控制器确定特定存储体是否填充有页面模式DRAM或扩展数据输出DRAM。 优选实施例还包括列地址选通状态机，其自动控制安装在主存储器中的两种类型的DRAM设备的定时要求，以快速有效地处理访问请求。
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6.发明授权Method and apparatus for determining memory types of a multi-type memory subsystem where memory of the different types are accessed using column control signals with different timing characteristics 失效用于确定使用具有不同定时特性的列控制信号来访问不同类型的存储器的多型存储器子系统的存储器类型的方法和装置公开(公告)号：US06505282B1
公开(公告)日：2003-01-07
申请号：US08821705
申请日：1997-03-19
IPC分类号： G06F1200
CPC分类号： G06F12/0684 , G06F13/1694
摘要： In a memory subsystem having a plurality of memory banks populated with up to a corresponding plurality of dynamic random access memory (DRAM) modules, the DRAM modules being of an extended data out type DRAM module or a page mode type DRAM module, ascertaining the type of DRAM module installed in populated ones of the plurality of memory banks. The DRAM type is determined by storing a predetermined value to a predetermined location in populated ones of the plurality of memory banks, and subsequently reading data from the predetermined location of populated ones of the plurality of memory banks using a page read control signal suitable for the extended data out type DRAM modules. If the data read corresponds to the predetermined value stored, an extended data out type DRAM module is identified.
摘要翻译： 在具有填充到相应的多个动态随机存取存储器（DRAM）模块的多个存储体的存储器子系统中，DRAM模块是扩展数据输出型DRAM模块或页模式型DRAM模块，确定类型 的DRAM模块安装在多个存储体中的填充的存储器中。 DRAM类型通过将预定值存储到多个存储体中的填充的存储体中的预定位置来确定，并且随后使用适合于所述多个存储体的页面读取控制信号从多个存储体中的填充的存储体的预定位置读取数据 扩展数据输出型DRAM模块。 如果数据读取对应于存储的预定值，则识别扩展数据输出型DRAM模块。
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公开(公告)号：US07469316B2
公开(公告)日：2008-12-23
申请号：US10364280
申请日：2003-02-10
申请人： James M. Dodd
发明人： James M. Dodd
CPC分类号： G06F12/0215
摘要： Machine-readable media, methods, and apparatus are described to issue transactions to a memory. In some embodiments, a memory controller may select pending transactions based upon selection criteria and may issue the selected transactions to memory. Further, the memory controller may close a page of the memory accessed by a write transaction in response to determining that the write transaction is the last write transaction of a series of one or more write transactions.
摘要翻译： 描述机器可读介质，方法和装置以向存储器发出事务。 在一些实施例中，存储器控制器可以基于选择标准来选择待处理的事务，并且可以将所选择的事务发布到存储器。 此外，响应于确定写入事务是一系列一个或多个写入事务的最后一个写入事务，存储器控制器可以关闭由写入事务访问的存储器的页面。
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公开(公告)号：US06981089B2
公开(公告)日：2005-12-27
申请号：US10037436
申请日：2001-12-31
CPC分类号： G06F13/4086
摘要： Methods and apparatus for a memory system using line termination circuits in each memory unit (e.g., integrated circuit memory device) are disclosed. The memory unit contains termination control logic that sets the state of a controllable termination circuit to control reflections on the data bus. The termination control logic determines the proper state for the termination circuit from the state of its memory unit, and in some cases, from the approximate state of the data bus as gleaned from commands decoded from the command/address bus. A termination configuration register on the unit can be used to define the appropriate termination state for each unit state and/or data bus state.
摘要翻译： 公开了在每个存储器单元（例如，集成电路存储器件）中使用线路终端电路的存储器系统的方法和装置。 存储器单元包含终止控制逻辑，其设置可控终端电路的状态以控制数据总线上的反射。 终止控制逻辑从其存储单元的状态确定终端电路的适当状态，并且在某些情况下，从从命令/地址总线解码的命令中收集到的数据总线的近似状态。 单元上的终端配置寄存器可用于为每个单元状态和/或数据总线状态定义适当的终止状态。
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公开(公告)号：US06925013B2
公开(公告)日：2005-08-02
申请号：US10786940
申请日：2004-02-24
CPC分类号： G06F13/1626 , G06F12/04
摘要： A data mask map may be programmed into a storage device in various ways. In one embodiment, the data mask is hardwired into a selection device to reorder either the data mask bits or the data chunks. In another embodiment, a data mask map is retrieved from a location in memory. In still another embodiment, the data mask map is determined through an algorithm.
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公开(公告)号：US07159066B2
公开(公告)日：2007-01-02
申请号：US10229655
申请日：2002-08-27
申请人： James M. Dodd
发明人： James M. Dodd
CPC分类号： G06F12/0215
摘要： Machine-readable media, methods, and apparatus are described which process memory transactions. In some embodiments, a processor requests an external memory controller to close a storage location of a memory associated with a first memory transaction based upon a relationship between the first memory transaction and a second memory transaction.
摘要翻译： 描述了处理存储器事务的机器可读介质，方法和装置。 在一些实施例中，处理器基于第一存储器事务和第二存储器事务之间的关系，请求外部存储器控制器关闭与第一存储器事务相关联的存储器的存储位置。
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