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1.发明授权System and method for controlling a memory array in an information handling system 失效用于控制信息处理系统中的存储器阵列的系统和方法公开(公告)号：US06412051B1
公开(公告)日：2002-06-25
申请号：US08757979
申请日：1996-11-27
IPC分类号： G06F1214
CPC分类号： G11C29/88 , G06F12/126 , G06F2212/1032 , G11C15/00 , G11C2029/0409
摘要： A system and method for allowing operation of a storage array after a failure within a set of an n-way set associative cache includes determining that there is a failure in a bit line in the storage array, setting a flag to inhibit access to the portion of the array accessed by the failing entity and storing and retrieving data from remaining portions of the array. The present invention is well adapted for use with n-way set associative cache storage arrays.
摘要翻译： 一种用于允许在一组n路组相关高速缓存中的故障之后存储阵列的操作的系统和方法包括确定存储阵列中位线中存在故障，设置禁止访问该部分的标志 由数据库的剩余部分存储和检索数据。 本发明适用于与n路组相关高速缓存存储阵列的使用。
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2.发明授权Data processing system having memory sub-array redundancy and method therefor 失效具有存储器子阵列冗余的数据处理系统及其方法
公开(公告)号：US6021512A
公开(公告)日：2000-02-01
申请号：US758410
申请日：1996-11-27
摘要： One or more redundant sub-arrays (324) are added to a memory (316-322) of a data processing system (300) to allow a manufacturer to compensate for defects introduced during the fabrication phase of a semiconductor device upon which it is implemented. Each of these redundant sub-arrays includes a separate and independent wordline decoder (202), bitline decoder (206), and input/output circuit (208). Furthermore, the memory to which the redundant sub-array is added is typically an on-chip memory which is organized into bit-slice sub-arrays. The bit-slice organization of the memory allows the redundant sub-array to be chained together with the on-chip memory. Data-in/data-out multiplexers are used to steer bit-slices of the data around the defective sub-arrays.
摘要翻译： 将一个或多个冗余子阵列（324）添加到数据处理系统（300）的存储器（316-322）中，以允许制造商补偿在其实现的半导体器件的制造阶段期间引入的缺陷 。 这些冗余子阵列中的每一个包括单独且独立的字线解码器（202），位线解码器（206）和输入/输出电路（208）。 此外，添加冗余子阵列的存储器通常是被组织成位片子阵列的片上存储器。 存储器的位片组织允许冗余子阵列与片上存储器一起链接。 数据输入/数据输出复用器用于控制有缺陷的子阵列周围的数据的位片。
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3.发明授权Cache sub-array method and apparatus for use in microprocessor integrated circuits 失效用于微处理器集成电路的缓存子阵列方法和装置
公开(公告)号：US5812418A
公开(公告)日：1998-09-22
申请号：US742221
申请日：1996-10-31
CPC分类号： G06F12/0893 , G06F15/7846 , G06F17/5068 , G11C5/025 , G06F2212/601
摘要： A cache sub-array method and apparatus for use in microprocessor integrated circuits. A processor unit is disposed within a central region of the microprocessor integrated circuit; a peripheral region is designated as a cache memory array region and surrounds the central region; a predetermined number of cache memory sub-arrays are placed in the peripheral region such that variable size cache memory arrays may be efficiently created. The cache memory sub-arrays contain a fixed fraction of a total cache word. The microprocessor integrated circuit itself has a modular cache memory array of variable size, and includes a central region having a processor unit disposed therein, a peripheral region designated as a cache memory array region surrounding the central region, and a predetermined number of cache memory sub-arrays disposed in the peripheral region such that the cache memory sub-arrays compose a modular cache memory array of variable size.
摘要翻译： 一种用于微处理器集成电路的缓存子阵列方法和装置。 处理器单元设置在微处理器集成电路的中心区域内; 外围区域被指定为高速缓冲存储器阵列区域并且围绕中心区域; 预定数量的高速缓存存储器子阵列被放置在外围区域中，使得可以有效地创建可变大小的高速缓存存储器阵列。 高速缓存存储器子阵列包含总高速缓存字的固定分数。 微处理器集成电路本身具有可变尺寸的模块化高速缓冲存储器阵列，并且包括设置在其中的处理器单元的中心区域，被指定为围绕中心区域的高速缓冲存储器阵列区域的外围区域和预定数量的高速缓冲存储器子 - 阵列设置在外围区域中，使得高速缓存存储器子阵列组成可变大小的模块化高速缓存存储器阵列。
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4.发明授权Apparatus and method of utilizing Alias Hit signals to detect errors within the real address tag arrays 有权利用别名命中信号检测真实地址标签阵列内的错误的装置和方法公开(公告)号：US06640293B1
公开(公告)日：2003-10-28
申请号：US09624105
申请日：2000-07-24
IPC分类号： G06F1200
CPC分类号： G06F11/0751 , G06F11/0772 , G06F11/0781 , G06F12/1063
摘要： A data processing system including a processor having a load/store unit and method for utilizing alias hit signals to detect errors within the read address tag arrays. Within a load store unit, implemented within a processor, a real address tag array is utilized to indicate when effective address aliasing occurs in a primary cache array. If aliasing occurs, Alias Hit signals are then used to clear any aliased entries. These Alias Hit signals can also be utilized to determine if there has been some type of failure within the real address tag array.
摘要翻译： 一种数据处理系统，包括具有加载/存储单元的处理器和用于利用别名命中信号来检测读取地址标签阵列内的错误的方法。在处理器内实现的加载存储单元中，使用实际地址标签阵列来指示 当主缓存阵列中发生有效的地址混叠时。 如果出现混叠，则使用别名命中信号来清除任何别名条目。 这些别名命中信号也可用于确定真实地址标签阵列中是否存在某种类型的故障。
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公开(公告)号：US6025741A
公开(公告)日：2000-02-15
申请号：US772643
申请日：1996-12-23
IPC分类号： G11C7/12 , G11C11/419 , H03K19/00
CPC分类号： G11C7/12 , G11C11/419
摘要： A circuit for conditionally restoring an execution unit in a computer processor, to reduce power consumption. Execution units, such as an arithmetic logic unit, shift/rotate unit, multiply unit, etc., have bits in transit that flow through a series of logic gates. These gates must be precharged after an operation has occurred to prepare the unit for the next operation. The conditional restore circuit evaluates either the data input to the execution unit, or the data output from the execution unit, to determine whether an operation has occurred. The precharge device for the execution is turned on only when the evaluation indicates that an operation has just occurred. The circuit includes an AND gate whose output controls the precharge device, and whose inputs include one line from the evaluation circuit, and one line for cycling (the system clock). In an embodiment wherein the execution unit has two operand multiplexers which receive the data input, the evaluation circuit includes two select line respectively connected to the multiplexers, and to inputs of the AND gate. In an alternative embodiment wherein the execution unit has data output in the form of a TRUE line and a COMPLEMENTARY line, the evaluation circuit includes a NOR gate means having a first input connected to said TRUE line, a second input connected to said COMPLEMENTARY line, and an output connected to said first input of the AND gate.
摘要翻译： 用于有条件地还原计算机处理器中的执行单元的电路，以减少功耗。 诸如算术逻辑单元，移位/旋转单元，乘法单元等的执行单元具有流经一系列逻辑门的传送位。 这些门必须在操作发生后进行预充电，以准备下一个操作的单元。 条件恢复电路评估输入到执行单元的数据或从执行单元输出的数据，以确定是否发生操作。 仅当评估指示刚刚发生操作时才执行用于执行的预充电装置。 该电路包括一个与门，其输出控制预充电装置，其输入包括来自评估电路的一条线和一条循环线（系统时钟）。 在其中执行单元具有接收数据输入的两个操作数复用器的实施例中，评估电路包括分别连接到多路复用器的两个选择线以及与门的输入。 在其中执行单元具有以TRUE线和COMPLEMENTARY线的形式的数据输出的替代实施例中，评估电路包括NOR门装置，其具有连接到所述TRUE线的第一输入端，连接到所述补充线路的第二输入端， 以及连接到与门的所述第一输入的输出。
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公开(公告)号：US5963486A
公开(公告)日：1999-10-05
申请号：US100354
申请日：1998-06-19
IPC分类号： G11C7/06 , G11C7/10 , G11C7/12 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/065 , G11C11/4096 , G11C7/1048 , G11C7/12
摘要： A bit switch circuit (10) includes an amplifier stage (11) and a plurality of input stages (23,33,43,53). Each input stage (23,33,43,53) is connected to receive as inputs the signals applied to a bit line pair associated with a memory array. Each input stage (23,33,43,53) is also associated with a common node (24,34,44,54), and a select transistor (T4, T5, T6, T7). Each select transistor (T4, T5, T6, T7) responds to a select input signal to couple the respective common node (24,34,44,54) to ground. This allows the sense amplifier (11) to respond to the data signals on the bit line pair (20,21,30,31,40,41,50,51) associated with the respective input stage (23,33,43,53).
摘要翻译： 位开关电路（10）包括放大器级（11）和多个输入级（23,33,43,53）。 每个输入级（23,33,43,53）被连接以接收施加到与存储器阵列相关联的位线对的信号作为输入。 每个输入级（23,33,43,53）也与公共节点（24,34,44,54）和选择晶体管（T4，T5，T6，T7）相关联。 每个选择晶体管（T4，T5，T6，T7）响应选择输入信号以将相应的公共节点（24,34,44,54）耦合到地。 这允许读出放大器（11）响应与相应输入级（23,33,43,53）相关联的位线对（20,21,30,31,40,41,50,51）上的数据信号 ）。
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公开(公告)号：US5953745A
公开(公告)日：1999-09-14
申请号：US758073
申请日：1996-11-27
CPC分类号： G11C29/78 , G06F12/0802 , G11C29/846
摘要： A set associative cache memory array includes redundant memory portions for use in the case of a defective portion of the memory. Information is stored within the defective portion of the memory array and an identical copy is stored within the redundant portion. Additionally, reading of the information is done from both the defective portion and the redundant portion. Selection of the information from either the defective portion or the redundant portion is made using programmable circuitry such as a fuse.
摘要翻译： 一组关联高速缓存存储器阵列包括用于在存储器的缺陷部分的情况下使用的冗余存储器部分。 信息存储在存储器阵列的缺陷部分内，并且相同的拷贝存储在冗余部分内。 此外，从缺陷部分和冗余部分两者进行信息的读取。 使用诸如保险丝的可编程电路来从缺陷部分或冗余部分中选择信息。
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8.发明授权Data processing system and method for generating memory control signals with clock skew tolerance 失效用于产生具有时钟偏差容限的存储器控制信号的数据处理系统和方法
公开(公告)号：US5870349A
公开(公告)日：1999-02-09
申请号：US959653
申请日：1997-10-28
IPC分类号： G11C7/10 , G11C11/412 , G11C7/00
CPC分类号： G11C7/1075 , G11C11/412
摘要： The data processing system of the present invention implements a multi-port memory cell, wherein the port functions are divided based on a timing cycle in which they may be accessed. For example, in one case, a first port may be utilized only for read operations and accessed only during a first portion of the timing cycle. Similarly, a second port may be used for read or write operations a and may be accessed only during a second portion of the timing cycle. To ensure that the multi-port memory cell functions correctly, both ports should not be accessed simultaneously. A circuit and method are implemented to ensure that both ports are not accessed simultaneously by implementing a delay function in a unique and useful manner.
摘要翻译： 本发明的数据处理系统实现了一个多端口存储单元，其中端口功能基于它们可被访问的定时周期被划分。 例如，在一种情况下，第一端口可以仅用于读取操作，并且仅在定时周期的第一部分期间被访问。 类似地，第二端口可以用于读取或写入操作a，并且可以仅在定时周期的第二部分期间被访问。 为了确保多端口存储单元功能正常，两个端口都不应同时访问。 实现电路和方法以通过以独特且有用的方式实现延迟功能来确保两个端口不被同时访问。
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9.发明授权
公开(公告)号：US5706237A
公开(公告)日：1998-01-06
申请号：US729823
申请日：1996-10-08
IPC分类号： G11C7/10 , G11C7/12 , G11C11/412 , G11C11/419 , G11C29/04 , G11C11/401
CPC分类号： G11C7/1048 , G11C11/4125 , G11C11/419 , G11C29/04 , G11C7/12
摘要： An improved self-restore circuit and method for restoring the output line of a dynamic logic circuit. The self-restore circuit includes two transistors connected in series between the output line and the reference voltage node. The first transistor activates after an evaluation of the output line, while the second transistor only activates subsequent to the activation of the first transistor and the completion of an evaluation cycle. The self-restore circuit reduces the power consumption and safeguards against any soft error hits, wherein the second transistor protects against any soft error hits by actively pulling up the output line to the appropriate voltage.
摘要翻译： 一种用于恢复动态逻辑电路的输出线的改进的自恢复电路和方法。 自恢复电路包括串联连接在输出线和参考电压节点之间的两个晶体管。 第一晶体管在输出线的评估之后激活，而第二晶体管仅在第一晶体管的激活和评估周期的完成之后激活。 自恢复电路降低功耗并防止任何软错误命中，其中第二晶体管通过主动地将输出线提升到适当的电压来防止任何软错误命中。
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公开(公告)号：US06243776B1
公开(公告)日：2001-06-05
申请号：US09114116
申请日：1998-07-13
IPC分类号： G06F1300
CPC分类号： G06F13/4072
摘要： A bus may be configured as either a single-ended mode bus or as a differential mode bus, depending on the system environment. The bus is configured in such a way that additional lines are not required, and so that substantially the same circuitry may be used for either single-ended mode or differential mode. Further, a selectable-mode driver may be connected to a non-selectable mode receiver, and vice versa. The invention may be implemented as a selectable driver, a selectable receiver, or a selectable driver/receiver pair. The apparatus and method of the present invention apply to both uni-directional and bi-directional bus implementations. The invention uses the same bus lines (i.e. wires) and substantially the same circuitry for both single-ended and differential modes of operation. When operating in single-ended mode, the data width of the bus is twice the data width as when operating in differential mode.
摘要翻译： 根据系统环境，总线可以配置为单端模式总线或差分模式总线。 总线被配置为不需要额外的线路，并且因此基本上相同的电路可以用于单端模式或差分模式。 此外，可选模式驱动器可以连接到不可选模式的接收器，反之亦然。 本发明可以被实现为可选择的驱动器，可选接收器或可选择的驱动器/接收器对。 本发明的装置和方法适用于单向和双向总线实现。 本发明使用相同的总线（即电线）和用于单端和差模操作模式的基本相同的电路。 当在单端模式下工作时，总线的数据宽度是在差分模式下工作时的数据宽度的两倍。
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