公开(公告)号：US06412051B1

公开(公告)日：2002-06-25

申请号：US08757979

申请日：1996-11-27

申请人： Brian R. Konigsburg ,  George McNeil Lattimore ,  John Stephen Muhich

发明人： Brian R. Konigsburg ,  George McNeil Lattimore ,  John Stephen Muhich

IPC分类号： G06F1214

CPC分类号： G11C29/88 ,  G06F12/126 ,  G06F2212/1032 ,  G11C15/00 ,  G11C2029/0409

摘要： A system and method for allowing operation of a storage array after a failure within a set of an n-way set associative cache includes determining that there is a failure in a bit line in the storage array, setting a flag to inhibit access to the portion of the array accessed by the failing entity and storing and retrieving data from remaining portions of the array. The present invention is well adapted for use with n-way set associative cache storage arrays.

摘要翻译： 一种用于允许在一组n路组相关高速缓存中的故障之后存储阵列的操作的系统和方法包括确定存储阵列中位线中存在故障，设置禁止访问该部分的标志 由数据库的剩余部分存储和检索数据。 本发明适用于与n路组相关高速缓存存储阵列的使用。

公开(公告)号：US6021512A

公开(公告)日：2000-02-01

申请号：US758410

申请日：1996-11-27

申请人： George McNeil Lattimore ,  Robert Paul Masleid ,  John Stephen Muhich

发明人： George McNeil Lattimore ,  Robert Paul Masleid ,  John Stephen Muhich

IPC分类号： G06F12/16 ,  G11C8/12 ,  G11C29/00 ,  G11C29/04 ,  G01R31/28

CPC分类号： G11C29/70 ,  G11C8/12

摘要： One or more redundant sub-arrays (324) are added to a memory (316-322) of a data processing system (300) to allow a manufacturer to compensate for defects introduced during the fabrication phase of a semiconductor device upon which it is implemented. Each of these redundant sub-arrays includes a separate and independent wordline decoder (202), bitline decoder (206), and input/output circuit (208). Furthermore, the memory to which the redundant sub-array is added is typically an on-chip memory which is organized into bit-slice sub-arrays. The bit-slice organization of the memory allows the redundant sub-array to be chained together with the on-chip memory. Data-in/data-out multiplexers are used to steer bit-slices of the data around the defective sub-arrays.

摘要翻译： 将一个或多个冗余子阵列（324）添加到数据处理系统（300）的存储器（316-322）中，以允许制造商补偿在其实现的半导体器件的制造阶段期间引入的缺陷 。 这些冗余子阵列中的每一个包括单独且独立的字线解码器（202），位线解码器（206）和输入/输出电路（208）。 此外，添加冗余子阵列的存储器通常是被组织成位片子阵列的片上存储器。 存储器的位片组织允许冗余子阵列与片上存储器一起链接。 数据输入/数据输出复用器用于控制有缺陷的子阵列周围的数据的位片。

公开(公告)号：US5812418A

公开(公告)日：1998-09-22

申请号：US742221

申请日：1996-10-31

申请人： George McNeil Lattimore ,  Robert Paul Masleid ,  John Stephen Muhich

发明人： George McNeil Lattimore ,  Robert Paul Masleid ,  John Stephen Muhich

IPC分类号： H01L21/822 ,  G06F12/08 ,  G06F15/78 ,  G06F17/50 ,  G11C5/02 ,  H01L21/82 ,  H01L27/04

CPC分类号： G06F12/0893 ,  G06F15/7846 ,  G06F17/5068 ,  G11C5/025 ,  G06F2212/601

摘要： A cache sub-array method and apparatus for use in microprocessor integrated circuits. A processor unit is disposed within a central region of the microprocessor integrated circuit; a peripheral region is designated as a cache memory array region and surrounds the central region; a predetermined number of cache memory sub-arrays are placed in the peripheral region such that variable size cache memory arrays may be efficiently created. The cache memory sub-arrays contain a fixed fraction of a total cache word. The microprocessor integrated circuit itself has a modular cache memory array of variable size, and includes a central region having a processor unit disposed therein, a peripheral region designated as a cache memory array region surrounding the central region, and a predetermined number of cache memory sub-arrays disposed in the peripheral region such that the cache memory sub-arrays compose a modular cache memory array of variable size.

摘要翻译： 一种用于微处理器集成电路的缓存子阵列方法和装置。 处理器单元设置在微处理器集成电路的中心区域内; 外围区域被指定为高速缓冲存储器阵列区域并且围绕中心区域; 预定数量的高速缓存存储器子阵列被放置在外围区域中，使得可以有效地创建可变大小的高速缓存存储器阵列。 高速缓存存储器子阵列包含总高速缓存字的固定分数。 微处理器集成电路本身具有可变尺寸的模块化高速缓冲存储器阵列，并且包括设置在其中的处理器单元的中心区域，被指定为围绕中心区域的高速缓冲存储器阵列区域的外围区域和预定数量的高速缓冲存储器子 - 阵列设置在外围区域中，使得高速缓存存储器子阵列组成可变大小的模块化高速缓存存储器阵列。

公开(公告)号：US5931957A

公开(公告)日：1999-08-03

申请号：US829669

申请日：1997-03-31

申请人： Brian R Konigsburg ,  John Stephen Muhich ,  Larry Edward Thatcher ,  Steven Wayne White

发明人： Brian R Konigsburg ,  John Stephen Muhich ,  Larry Edward Thatcher ,  Steven Wayne White

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F11/00 ,  G06F9/30

CPC分类号： G06F9/30043 ,  G06F9/3834 ,  G06F9/3861

摘要： To support load instructions which execute out-of-order with respect to store instructions, a mechanism is implemented to detect (and correct) the occurrences where a load instruction executed prior to a logically prior store instruction, and where the load instruction received data for the location prior to being modified by the store instruction, and the correct data for the load instruction included bytes from the store instruction. Additionally, to execute store instructions out-of-order with respect to load instructions, a mechanism is implemented to keep a store instruction from destroying data that will be used by a logically earlier load instruction. Further, to support load instructions that are executed out-of-order with respect to each other, a mechanism is implemented to insure that any pair of load instructions (which access at least one byte in common) return data consistent with executing the load instructions in order.

摘要翻译： 为了支持关于存储指令执行无序的加载指令，实现了一种机制来检测（和校正）在逻辑上先前的存储指令之前执行的加载指令的发生，并且其中加载指令接收数据为 由存储指令修改之前的位置，以及加载指令的正确数据，包括来自存储指令的字节。 另外，为了执行与加载指令无序的存储指令，实现了一种机制来保持存储指令不会破坏由逻辑上较早的加载指令使用的数据。 此外，为了支持相对于彼此执行的无序执行的加载指令，实现一种机制以确保任何一对加载指令（其访问至少一个共同的字节）返回数据与执行加载指令一致 为了。

公开(公告)号：US6021467A

公开(公告)日：2000-02-01

申请号：US713056

申请日：1996-09-12

申请人： Brian R. Konigsburg ,  John Stephen Muhich ,  Larry Edward Thatcher ,  Steven Wayne White

发明人： Brian R. Konigsburg ,  John Stephen Muhich ,  Larry Edward Thatcher ,  Steven Wayne White

IPC分类号： G06F12/08

CPC分类号： G06F12/0888 ,  G06F12/0859 ,  G06F12/0897 ,  Y02B60/1225

摘要： An apparatus and method for processing multiple cache misses to a single cache line in an information handling system which includes a miss queue for storing requests for data not located in a level one cache and a comparator for comparing requests for data stored in the miss queue to determine if there are multiple requests for data located in the same cache line of a level two cache. Each new request for data from the same cache line of the level two cache as an older original request for data in the miss queue is marked as a load hit reload. The requests marked as load hit reloads are then grouped together with the matching original request and forwarded together to the level two cache wherein the original request requests the data from level two cache. The load hit reload requests do not access level two cache but instead bypass access of level two cache by extracting data from the cache line outputted from level two cache for the matching original request. The present invention reduces the number of accesses to the level two cache and allows data requests to be satisfied in parallel versus serially when multiple successive level one cache misses occur.

摘要翻译： 一种用于处理信息处理系统中的多个高速缓存未命中到单个高速缓存行的装置和方法，该信息处理系统包括用于存储不在一级高速缓存中的数据的请求的未命中队列，以及比较器，用于将存储在所述未命中队列中的数据的请求与 确定是否存在针对二级缓存的同一高速缓存行中的数据的多个请求。 来自与二级缓存相同的高速缓存行的数据的新请求作为旧队列中的数据的较早原始请求被标记为加载命中重新加载。 标记为加载命中重载的请求随后与匹配的原始请求分组在一起并一起转发到二级缓存，其中原始请求请求来自二级缓存的数据。 加载命中重新加载请求不访问二级缓存，而是通过从匹配的原始请求的二级缓存输出的高速缓存行中提取数据来绕过二级缓存的访问。 本发明减少对二级高速缓存的访问次数，并且允许当发生多个连续一级高速缓存未命中时并行地对数据请求进行满足。

公开(公告)号：US5802571A

公开(公告)日：1998-09-01

申请号：US734318

申请日：1996-10-21

申请人： Brian R. Konigsburg ,  John Stephen Muhich ,  Steven Wayne White

发明人： Brian R. Konigsburg ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F12/12 ,  G06F12/08

CPC分类号： G06F12/0859

摘要： An age-based arbitration scheme for enforcing data coherency in an information handling system is disclosed. As loads and stores access a cache, if a cache miss occurs, a miss request is generated and tagged with the cycle or age in which the miss is detected. If a castout is required, it is also tagged with the cycle in which the load or store access occurred, and the line being replaced or cast out is marked as being invalid in that level of hierarchy. The arbitration rules for the next level of memory hierarchy are defined such that all requests that are generated during a particular cycle are given priority over all of the requests generated during any subsequent cycle. As a result, if a load miss occurs for a cache line which is present in the castout buffer, the castout request tagged with an earlier age will be arbitrated into the next memory hierarchy level prior to the arrival of the newly generated miss requests. The age-based arbitration scheme can also be used for multiple cache accesses occurring in parallel.

摘要翻译： 公开了一种用于在信息处理系统中执行数据一致性的基于年龄的仲裁方案。 当加载和存储访问缓存时，如果发生高速缓存未命中，则会生成错误请求并标记检测到未命中的周期或年龄。 如果需要castout，它也会被标记为发生加载或存储访问的循环，并且被替换或丢弃的行在该级别的级别中被标记为无效。 定义下一级存储器层级的仲裁规则，使得在特定周期期间生成的所有请求优先于在任何后续周期期间生成的所有请求。 结果，如果对于存在于转储缓冲器中的高速缓存行发生负载缺失，则在新生成的未命中请求到达之前，具有较早年龄的标记的转换请求将被仲裁到下一个存储器层级中。 基于年龄的仲裁方案也可以用于并行发生的多个高速缓存访​​问。

公开(公告)号：US06002285A

公开(公告)日：1999-12-14

申请号：US654361

申请日：1996-05-28

申请人： John Stephen Muhich ,  Quan Nguyen

发明人： John Stephen Muhich ,  Quan Nguyen

IPC分类号： H03K3/356 ,  H03K17/693

CPC分类号： H03K3/356121 ,  H03K17/693 ,  H03K3/356156

摘要： An output signal is output to a selected one of first and second output nodes in response to an event in which a control node transitions from a first logic state to a second logic state. The selected one of the first and second output nodes is selected in response to a logic state of an input node during the event. A minimum setup time for the logic state of the input node to be stable before the control node transitions to the second logic state is shorter than a minimum time for inverting the logic state of the input node.

摘要翻译： 响应于控制节点从第一逻辑状态转换到第二逻辑状态的事件，将输出信号输出到第一和第二输出节点中的所选择的一个。 在事件期间响应于输入节点的逻辑状态选择第一和第二输出节点中选择的一个。 在控制节点转换到第二逻辑状态之前，输入节点的逻辑状态为稳定的最小建立时间短于用于反转输入节点的逻辑状态的最小时间。

公开(公告)号：US5872950A

公开(公告)日：1999-02-16

申请号：US829670

申请日：1997-03-31

申请人： David Stephen Levitan ,  John Stephen Muhich

发明人： David Stephen Levitan ,  John Stephen Muhich

IPC分类号： G06F9/38

CPC分类号： G06F9/3855 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3863

摘要： A method and apparatus for managing register renaming in an information handling system that supports out-of-order and speculative instruction execution. Register entries are stored in architected registers, and rename entries are stored in rename registers. Register and rename entries are transferred between the rename and architected registers in response to dispatch of instructions or upon the occurrence of a canceling event, such as a mispredicted branch instruction or an interrupt condition. Rename entries are stored in the rename registers in a round robin fashion and tagged by age. Age order of the rename entries is determined without keeping the rename entries in age order through the method of shifting rename entries to the next rename register each time a rename entry is removed from a rename register. By eliminating shifting of rename entries to maintain age order, a power savings is realized.

摘要翻译： 一种在信息处理系统中管理寄存器重命名的方法和装置，其支持乱序和推测性指令执行。 注册条目存储在架构化的寄存器中，重命名条目存储在重命名寄存器中。 响应于指令的发送或发生诸如错误的分支指令或中断条件的取消事件，在重命名和架构化寄存器之间传送寄存器和重命名条目。 重命名条目以循环方式存储在重命名寄存器中，并按年龄标记。 确定重命名条目的年龄顺序，而不必通过将重命名条目移动到重命名寄存器的每个重命名条目从重命名寄存器中删除的方式将重命名条目按照年龄顺序进行保存。 通过消除重命名条目的移动以维持年龄顺序，实现了省电。

公开(公告)号：US5870582A

公开(公告)日：1999-02-09

申请号：US829671

申请日：1997-03-31

申请人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

发明人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F9/38

CPC分类号： G06F9/3855 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3863

摘要： In a method and apparatus for allocating processor resources in a data processing system, instructions are dispatched and tagged for processing. A processor resource snoops to obtain execution results for the tagged instructions. Such an instruction is logically "finished" in response to determining that it will not cause an interrupt (which includes not changing the sequence of completing instructions), and "completed" in response to finishing all earlier dispatched instructions. Information is entered for such an instructions in rename buffer in response to the instruction targeting an architected register, and such a rename buffer entry is released in response to completing the entry's instruction. The rename buffer may comprise a history buffer. Also, information for the instructions is entered in a completion queue in response to dispatching the instructions, and the queue entry for such an instruction is released in response to completion of the instruction. Also, the instructions are grouped, a group having solely a single interruptible instruction, and further including non-interruptible instructions dispatched following the interruptible instruction. Thus, there may be numerous non-interruptible instructions in such a group. Such an interruptible instruction is logically "finished" in response to determining that it will not cause an interrupt, and "completed" in response to finishing all earlier dispatched instructions. Such a non-interruptible instruction is logically "finished" and "completed" in response to completion of its associated interruptible instruction, so that such a non-interruptible instruction may complete before it is dispatched.

摘要翻译： 在用于在数据处理系统中分配处理器资源的方法和装置中，调度和标记用于处理的指令。 处理器资源被窥探以获得标记指令的执行结果。 响应于确定不会导致中断（其不包括改变完成指令的顺序），并且响应于完成所有先前分派的指令而“完成”，这样的指令在逻辑上“完成”。 响应于针对架构化寄存器的指令，在重命名缓冲器中输入这样的指令的信息，并且响应于完成条目的指令而释放这样的重命名缓冲器条目。 重命名缓冲器可以包括历史缓冲器。 此外，响应于分派指令，将指令的信息输入到完成队列中，并且响应于指令的完成而释放这样的指令的队列条目。 此外，指令被分组，仅具有单个可中断指令的组，并且还包括在可中断指令之后分派的不可中断指令。 因此，在这样的组中可能存在许多不可中断的指令。 这种可中断指令在逻辑上“完成”以响应于确定它不会引起中断，并且响应于完成所有先前分派的指令而“完成”。 响应于其相关联的可中断指令的完成，这种不可中断指令被逻辑地“完成”和“完成”，使得这种不可中断指令可以在其被分派之前完成。

公开(公告)号：US5864341A

公开(公告)日：1999-01-26

申请号：US761875

申请日：1996-12-06

申请人： Troy Neal Hicks ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

发明人： Troy Neal Hicks ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3891 ,  G06F9/3824 ,  G06F9/3853 ,  G06F9/3885

摘要： The present invention is directed to a method and apparatus for dispatching instructions in an information handling system. A pre-execution queue stores instructions, and at least one execution cluster is operably coupled to the pre-execution queue. An execution cluster comprises an early execution unit for executing a first instruction dispatched from the pre-execution queue to generate and forward a first result and a late execution unit for executing a second instruction dispatched from the pre-execution queue to generate and forward a second result after the first execution unit forwards the first result. The invention further includes circuitry operably associated with the pre-execution queue, and a method for prioritizing the order in which the instructions in the pre-execution queue are dispatched to the execution cluster.

摘要翻译： 本发明涉及一种用于在信息处理系统中调度指令的方法和装置。 预执行队列存储指令，并且至少一个执行群集可操作地耦合到预执行队列。 执行群包括一个早期执行单元，用于执行从预执行队列发出的第一指令，以产生和转发第一结果;以及后期执行单元，用于执行从预执行队列发出的第二指令，以产生和转发第二个 第一执行单元转发第一个结果后的结果。 本发明还包括可操作地与预执行队列相关联的电路，以及用于将预执行队列中的指令分派到执行群集的顺序的优先级的方法。