公开(公告)号：US07058120B1

公开(公告)日：2006-06-06

申请号：US10051222

申请日：2002-01-18

申请人： Jinghui Lu ,  Shahriar Rokhsaz ,  Stephen D. Anderson ,  Michael A. Nix ,  Ahmed Younis ,  Michael Ren Kent ,  Yvette P. Lee ,  Firas N. Abughazaleh ,  Brian T. Brunn ,  Moises E. Robinson ,  Kazi S. Hossain

发明人： Jinghui Lu ,  Shahriar Rokhsaz ,  Stephen D. Anderson ,  Michael A. Nix ,  Ahmed Younis ,  Michael Ren Kent ,  Yvette P. Lee ,  Firas N. Abughazaleh ,  Brian T. Brunn ,  Moises E. Robinson ,  Kazi S. Hossain

IPC分类号： H03K11/00 ,  H04L25/60 ,  H04L25/64

CPC分类号： H03L7/093 ,  H03K5/1565 ,  H03M9/00 ,  H04L7/0004 ,  H04L7/033 ,  H04W4/18

摘要： A transceiver includes a receiver section and a transmitter section. The receiver section includes a clocking circuit, a serial-to-parallel module, and compensation. The transmitter section includes a clocking circuit, parallel-to-serial module, and compensation. The compensation within the receiver section and transmitter section compensates for integrated circuit (IC) processing limits and/or integrated circuit (IC) fabrication limits within the clocking circuits, serial-to-parallel module, and parallel-to-serial module that would otherwise limit the speed at which the transceiver could transport data.

摘要翻译： 收发机包括接收机部分和发射机部分。 接收器部分包括时钟电路，串行到并行模块和补偿。 发射机部分包括时钟电路，并行到串行模块和补偿。 接收器部分和发射器部分内的补偿补偿了时钟控制电路，串行到并行模块和并行到串行模块的集成电路（IC）处理限制和/或集成电路（IC）制造限制，否则 限制收发器可以传输数据的速度。

公开(公告)号：US07224760B1

公开(公告)日：2007-05-29

申请号：US10421512

申请日：2003-04-22

申请人： Shahriar Rokhsaz ,  Moises E. Robinson ,  Ahmed Younis ,  Brian T. Brunn

发明人： Shahriar Rokhsaz ,  Moises E. Robinson ,  Ahmed Younis ,  Brian T. Brunn

IPC分类号： H03D3/24

CPC分类号： H04L7/0331 ,  H03D13/003 ,  H03L7/087 ,  H03L7/0896 ,  H03L7/091 ,  H03L7/10

摘要： A high-speed, wide bandwidth data detection circuit includes a phase detection module, a data detection module, a loop filter, and a voltage controlled oscillator. The phase detection module is operably coupled to produce a controlled current based on a current mode mathematical manipulation of differences between an incoming data stream and a recovered clock. The phase detection module performs the current mode mathematical manipulations and produces the controlled current in the current domain. The data detection module is operably coupled to produce the detected data based on the incoming data stream and the recovered clock. The loop filter is operably coupled to convert the controlled current into a controlled voltage. The voltage controlled oscillator is operably coupled to convert the control voltage into the recovered clock.

摘要翻译： 高速，宽带宽数据检测电路包括相位检测模块，数据检测模块，环路滤波器和压控振荡器。 相位检测模块可操作地耦合以基于对输入数据流和恢复的时钟之间的差异的当前模式数学操作产生受控电流。 相位检测模块执行当前模式的数学操作并产生当前域中的受控电流。 数据检测模块可操作地耦合以基于输入数据流和恢复的时钟产生检测到的数据。 环路滤波器可操作地耦合以将受控电流转换成受控电压。 压控振荡器可操作地耦合以将控制电压转换成恢复的时钟。

公开(公告)号：US06977959B2

公开(公告)日：2005-12-20

申请号：US10346435

申请日：2003-01-17

申请人： Brian T. Brunn ,  Ahmed Younis ,  Shahriar Rokhsaz

发明人： Brian T. Brunn ,  Ahmed Younis ,  Shahriar Rokhsaz

IPC分类号： H03D13/00 ,  H03L7/087 ,  H03L7/089 ,  H03L7/10 ,  H04L7/033 ,  H04B1/38 ,  H03D3/24

CPC分类号： H04L7/0331 ,  H03D13/003 ,  H03L7/087 ,  H03L7/0896 ,  H03L7/091 ,  H03L7/10

摘要： A clock recovery circuit that operates at a clock speed equal to one-half the input data rate is presented. The clock recovery circuit uses dual input latches to sample the incoming serial data on both the rising edge and falling edge of a half-rate clock signal to provide equivalent full data rate clock recovery. The clock recovery circuit functions to maintain the half-rate clock transitions in the center of the incoming serial data bits. The clock recovery circuit includes a phase detector, charge pump, controlled oscillation module and a feedback module. The phase detector produces information on the phase and data transitions in the incoming data signal to the charge pump. Generally, the circuit is delay insensitive and receives phase and transition information staggered relative to each other.

摘要翻译： 提出了以等于输入数据速率的一半的时钟速度工作的时钟恢复电路。 时钟恢复电路使用双输入锁存器在半速率时钟信号的上升沿和下降沿对采样的串行数据进行采样，以提供等效的全数据速率时钟恢复。 时钟恢复电路用于保持输入串行数据位中心的半速率时钟转换。 时钟恢复电路包括相位检测器，电荷泵，受控振荡模块和反馈模块。 相位检测器产生关于输入数据信号中的相位和数据转换到电荷泵的信息。 通常，电路是延迟不敏感的，并且相对于彼此交错地接收相位和转换信息。

公开(公告)号：US07142622B1

公开(公告)日：2006-11-28

申请号：US10421248

申请日：2003-04-22

申请人： Brian T. Brunn ,  Ahmed Younis

发明人： Brian T. Brunn ,  Ahmed Younis

IPC分类号： H03D3/24

CPC分类号： H03D13/004

摘要： A multiplying phase detector includes a 1st multiplier, a 2nd multiplier and a phase error generation module. The 1st multiplier is operably coupled to multiple an incoming data stream, which is a random data pattern, with a 1st clock, which is in-phase with the incoming stream of data and is one-half the rate of the incoming stream of data, to produce a 1st product. In this instance, the 1st product represents missing transitions in the incoming stream of data. The 2nd multiplier is operably coupled to multiply the 1st product with the incoming data stream to produce a modified stream of data. The phase error generation module is operably coupled to generate a phase error based on the modified stream of data and a 2nd clock, where the phase error represents a phase offset between the modified stream of data and the 2nd clock.

摘要翻译： 乘法相位检测器包括1乘法器，2乘法器和相位误差产生模块。 1＆lt; ST＆gt;乘法器可操作地耦合到具有1秒时钟的多个输入数据流，其是随机数据模式，其与进入流同步 的数据，并且是传入数据流的一半速率，以产生1 ^{ST 产品。 在这种情况下，1＆lt; ST＆gt;产品表示输入的数据流中的丢失的转换。 2乘法器乘法器可操作地耦合以将第一产品与输入数据流相乘以产生经修改的数据流。 相位误差产生模块可操作地耦合以产生基于经修改的数据流和第二时钟的相位误差，其中相位误差表示修改的数据流与第二时钟之间的相位偏移 nd 时钟。}

公开(公告)号：US07436216B1

公开(公告)日：2008-10-14

申请号：US11452858

申请日：2006-06-14

申请人： Brian T. Brunn ,  Michael A. Nix ,  Ahmed Younis

发明人： Brian T. Brunn ,  Michael A. Nix ,  Ahmed Younis

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F3/4521 ,  H03F3/45632 ,  H03F2203/45101 ,  H03F2203/45354 ,  H03F2203/45588 ,  H03F2203/45592 ,  H03F2203/45616 ,  H03F2203/45681

摘要： A method and apparatus for combining an alternating current (AC) coupling technique with a low frequency restoration technique to provide AC coupling with low frequency restoration of the attenuated low frequency content. The low frequency restoration circuit operates to extract low frequency information prior to being high-pass filtered by the AC coupling circuit. The low frequency restoration circuit then buffers the low frequency information through a low frequency restoration amplifier, applies a programmable common mode voltage to the buffered, low frequency information, and then restores the buffered, common mode adjusted, low frequency information to the output of the AC coupling circuit.

摘要翻译： 一种用于将交流（AC）耦合技术与低频恢复技术组合以提供与所述衰减低频内容的低频恢复的AC耦合的方法和装置。 在由AC耦合电路进行高通滤波之前，低频恢复电路用于提取低频信息。 然后，低频恢复电路通过低频恢复放大器缓冲低频信息，将可编程共模电压施加到缓冲的低频信息，然后将缓冲的共模调制的低频信息恢复到 交流耦合电路。

公开(公告)号：US06501339B1

公开(公告)日：2002-12-31

申请号：US09927146

申请日：2001-08-10

申请人： Ahmed Younis ,  Moises E. Robinson ,  Michael A. Nix ,  Brian T. Brunn

发明人： Ahmed Younis ,  Moises E. Robinson ,  Michael A. Nix ,  Brian T. Brunn

IPC分类号： H03B524

CPC分类号： H03L7/0995 ,  H03K3/0315 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/18

摘要： Electronic devices are typically coupled together to operate as systems that require the communication of data from one device to another. Many such devices include a ring oscillator, a circuit that generates one or more oscillating signals using a series of interconnected delay circuits. One problem with conventional ring oscillators concerns differences in the signal paths between the delay circuits. Accordingly, the present inventors devised several oscillators having unique layouts, which reduce differences in the signal paths between delay circuits. One exemplary oscillator includes a sequence of delay circuits having input-output connections between at least two pairs of non-adjacent delay circuits. Another exemplary oscillator provides two groups of delay circuits with a bus between the two groups, intercoupling the circuits. And, another exemplary oscillator arranges three or more delay circuits to form a closed loop. Applications for these oscillators include not only receivers, transmitters, and transceivers, but also programmable integrated circuits, electronic devices, and systems.

摘要翻译： 电子设备通常耦合在一起以作为需要从一个设备到另一个设备的数据通信的系统进行操作。 许多这样的设备包括环形振荡器，使用一系列互连的延迟电路产生一个或多个振荡信号的电路。 常规环形振荡器的一个问题涉及延迟电路之间的信号路径的差异。 因此，本发明人设计了具有独特布局的几个振荡器，其减小延迟电路之间的信号路径的差异。 一个示例性振荡器包括在至少两对非相邻延迟电路之间具有输入 - 输出连接的延迟电路序列。 另一个示例性振荡器提供两组延迟电路，其中两组之间的总线相互耦合。 并且，另一示例性振荡器布置三个或更多个延迟电路以形成闭环。 这些振荡器的应用不仅包括接收器，发射器和收发器，还包括可编程集成电路，电子设备和系统。

公开(公告)号：US06912698B1

公开(公告)日：2005-06-28

申请号：US10155301

申请日：2002-05-23

申请人： Brian T. Brunn ,  Brian K. Seemann

发明人： Brian T. Brunn ,  Brian K. Seemann

IPC分类号： G01R31/28 ,  G06F17/50

CPC分类号： G01R31/2884

摘要： Integrated circuits, key components in thousands of products, frequently include thousands and even millions of microscopic transistors and other electrical components. Because of difficulties and costs of fabricating these circuits, circuit designers sometimes ask fabricators to produce skew lots for testing and predicting manufacturing yield. However, conventional skew lots for CMOS circuits, which are based on increasing or decreasing transistor transconductance, are not very useful in testing certain types of analog circuits, such as oscillators. Accordingly, the present inventors developed a new type of skew lot, based on increasing or decreasing gate-to-source capacitance of transistors, or more generally a transistor characteristic other than transconductance. This new type of skew lot is particularly suitable for simulating, testing, and/or making yield predictions for oscillators and other CMOS analog circuits.

摘要翻译： 集成电路，成千上万个产品的关键组件，经常包括数千甚至数百万的微观晶体管和其他电气元件。 由于制造这些电路的困难和成本，电路设计师有时要求制造商生产偏斜批次用于测试和预测制造产量。 然而，基于增加或减少晶体管跨导的CMOS电路的常规偏移批次在测试某些类型的模拟电路（例如振荡器）中不是非常有用的。 因此，本发明人基于晶体管的栅极 - 源极电容的增加或减小，或更通常地是跨导以外的晶体管特性，开发了新型的偏移批次。 这种新型的偏移批次特别适用于振荡器和其他CMOS模拟电路的模拟，测试和/或产量预测。

公开(公告)号：US07619298B1

公开(公告)日：2009-11-17

申请号：US11095812

申请日：2005-03-31

申请人： Firas N. Abughazaleh ,  Brian T. Brunn

发明人： Firas N. Abughazaleh ,  Brian T. Brunn

IPC分类号： H01L27/108

CPC分类号： H01L21/76 ,  H01L27/0629 ,  H01L27/0676 ,  H01L27/0805 ,  H01L28/40

摘要： A method and apparatus for reducing parasitic capacitance. A P-well blocked layer is formed directly beneath a parasitic device. The P-well blocked layer significantly increases the resistance underneath the parasitic device. The resistance of the P-well blocked layer, in effect, partially disconnects the parasitic device from the ground terminal to minimize the effective capacitive impedance that is added to the total termination impedance.

摘要翻译： 一种降低寄生电容的方法和装置。 P阱封闭层直接形成在寄生器件的正下方。 P阱阻挡层显着增加寄生器件下方的电阻。 实际上，P阱阻挡层的电阻实际上部分地将寄生器件与接地端子断开，以最小化添加到总终端阻抗的有效电容阻抗。

公开(公告)号：US07184466B1

公开(公告)日：2007-02-27

申请号：US10243411

申请日：2002-09-12

申请人： Brian K. Seemann ,  Brian T. Brunn ,  Normand T. Lemay, Jr. ,  Daniel J. Ferris, III ,  Thomas Anthony Lee ,  James M. Simkins ,  David B. Squires

发明人： Brian K. Seemann ,  Brian T. Brunn ,  Normand T. Lemay, Jr. ,  Daniel J. Ferris, III ,  Thomas Anthony Lee ,  James M. Simkins ,  David B. Squires

IPC分类号： H04B1/38

CPC分类号： H04B1/406 ,  H04B1/0003

摘要： A data conveyance integrated system that can be utilized in a base station and/or end user devices in a wireless communication system. The integrated system includes first and second integrated circuits (ICs). The first IC includes a first serial-deserial (SERDES) module, a transmit radio frequency module, and a receive radio frequency module. The transmit and receive radio frequency modules provide the wireless communication between the base stations and end user devices. The second IC includes a second SERDES module and a programmable logic fabric programmed to implement one or more wireless communication functions. Accordingly, the programmable logic fabric generates outbound digital signals from data (e.g., video, audio, control, or text data) provided to the device, and/or processes inbound digital signals to recapture the originally transmitted data. Thus, base stations and/or end user devices within a wireless communication system can be readily reconfigured.

摘要翻译： 一种可在无线通信系统中的基站和/或终端用户设备中使用的数据传输集成系统。 集成系统包括第一和第二集成电路（IC）。 第一IC包括第一串并联（SERDES）模块，发射射频模块和接收射频模块。 发射和接收射频模块提供基站和终端用户设备之间的无线通信。 第二IC包括被编程为实现一个或多个无线通信功能的第二SERDES模块和可编程逻辑结构。 因此，可编程逻辑结构从提供给设备的数据（例如，视频，音频，控制或文本数据）生成出站数字信号，和/或处理入站数字信号以重新捕获原始传输的数据。 因此，可以容易地重新配置无线通信系统内的基站和/或终端用户设备。

公开(公告)号：US07092689B1

公开(公告)日：2006-08-15

申请号：US10660235

申请日：2003-09-11

申请人： Charles W. Boecker ,  Brian T. Brunn

发明人： Charles W. Boecker ,  Brian T. Brunn

IPC分类号： H04B1/06

CPC分类号： H04L27/0014 ,  H03L7/0896 ,  H03L7/0898 ,  H04L2027/0055 ,  H04L2027/0067

摘要： Adjustment circuitry in a phase-locked loop (PLL) adjusts a sampling point to any desired location within a bit period of each bit of received high-speed serial data. The adjustment circuitry, responsive to program control, selectively adds current portions to a charge pump error current output thereby adjusting a feedback signal frequency to shift the serial data sampling point. A plurality of current mirror devices is scaled, with respect to a reference current device, to provide ΔI current portions. A current control module controls the current portions magnitude and a sign of the current portions. The adjustment circuitry further controls charge pump programmable current sources in order to set a desired operating point of the PLL. The programmable current sources are controlled by a bias voltage and a plurality of selectable serial and parallel coupled resistors.