公开(公告)号：US20150228668A1

公开(公告)日：2015-08-13

申请号：US14192798

申请日：2014-02-27

Applicant: BROADCOM CORPORATION

Inventor： Shom Surendran Ponoth ,  Changyok Park

IPC: H01L27/12 ,  H01L21/762

CPC classification number: H01L27/1207 ,  H01L21/76224 ,  H01L21/845 ,  H01L27/1211

Abstract: A method for forming a dielectric-isolated bulk fin field-effect transistor (finFET) device includes forming a second isolation layer over a first structure including multiple partially exposed fins and horizontal areas including a first isolation layer. The second isolation layer is removed from horizontal areas of a first portion of the first structure. An oxide layer is formed under the fins of the first portion of the first structure. The second isolation layer is removed in order to expose the partially exposed fins and horizontal areas of the first structure to form a second structure, on which gate regions are formed.

Abstract translation: 一种用于形成介质隔离体鳍片场效应晶体管（finFET）器件的方法包括在包括多个部分暴露的鳍片和包括第一隔离层的水平区域的第一结构上形成第二隔离层。 第二隔离层从第一结构的第一部分的水平区域移除。 在第一结构的第一部分的翅片下方形成氧化物层。 去除第二隔离层以暴露第一结构的部分暴露的翅片和水平区域以形成其上形成有栅极区域的第二结构。

公开(公告)号：US09209202B2

公开(公告)日：2015-12-08

申请号：US14192798

申请日：2014-02-27

Applicant: BROADCOM CORPORATION

Inventor： Shom Surendran Ponoth ,  Changyok Park

IPC: H01L21/84 ,  H01L27/12 ,  H01L21/762

CPC classification number: H01L27/1207 ,  H01L21/76224 ,  H01L21/845 ,  H01L27/1211

Abstract: A method for forming a dielectric-isolated bulk fin field-effect transistor (finFET) device includes forming a second isolation layer over a first structure including multiple partially exposed fins and horizontal areas including a first isolation layer. The second isolation layer is removed from horizontal areas of a first portion of the first structure. An oxide layer is formed under the fins of the first portion of the first structure. The second isolation layer is removed in order to expose the partially exposed fins and horizontal areas of the first structure to form a second structure, on which gate regions are formed.

Abstract translation: 一种用于形成介质隔离体鳍片场效应晶体管（finFET）器件的方法包括在包括多个部分暴露的鳍片和包括第一隔离层的水平区域的第一结构上形成第二隔离层。 第二隔离层从第一结构的第一部分的水平区域移除。 在第一结构的第一部分的翅片下方形成氧化物层。 去除第二隔离层以暴露第一结构的部分暴露的翅片和水平区域以形成其上形成有栅极区域的第二结构。

公开(公告)号：US20150200196A1

公开(公告)日：2015-07-16

申请号：US14173744

申请日：2014-02-05

Applicant: BROADCOM CORPORATION

Inventor： Shom Surendran Ponoth ,  Akira Ito ,  Changyok Park

IPC: H01L27/112 ,  H01L29/66 ,  H01L23/525 ,  H01L29/78

CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L23/5252 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An anti-fuse device for fin field-effect transistor (finFET) technology includes a dummy gate, an electrically conductive contact, and a diffusion contact. The dummy gate is formed over an end-corner of a fin. The electrically conductive contact is disposed on a portion of the dummy gate and can be used as a first electrode of the device. The diffusion contact is disposed over the fin and can be used as a second electrode of the device.

Abstract translation: 用于鳍状场效应晶体管（finFET）技术的反熔丝器件包括虚拟栅极，导电触点和扩散接触。 虚拟门形成在翅片的端角上。 导电触点设置在虚拟栅极的一部分上，并且可以用作该器件的第一电极。 扩散接触件设置在翅片上并且可以用作该器件的第二电极。

公开(公告)号：US09941271B2

公开(公告)日：2018-04-10

申请号：US14069174

申请日：2013-10-31

Applicant: BROADCOM CORPORATION

Inventor： Shom Surendran Ponoth ,  Changyok Park ,  Akira Ito

IPC: H01L27/10 ,  H01L21/70 ,  H01L27/088 ,  H01L27/06

CPC classification number: H01L27/0629

Abstract: A fin-shaped field-effect transistor device is provided. The fin-shaped field effect transistor device may include a semiconductor substrate having a top and a bottom surface. The fin-shaped field effect transistor device may also include a fin structure disposed on the top surface of the semiconductor substrate, where the fin structure includes a first sidewall and a second sidewall opposite of the first sidewall. The first sidewall is adjacent to a first region of the top surface of the semiconductor substrate and the second sidewall is adjacent to a second region of the top surface of the semiconductor substrate. The fin-shaped field effect transistor device may also include an insulation layer disposed above the fin structure and the first and second regions of the top surface. The fin-shaped field effect transistor device may also include a conductor structure disposed above and adjacent to the insulation layer.

公开(公告)号：US09337188B2

公开(公告)日：2016-05-10

申请号：US14072723

申请日：2013-11-05

Applicant: Broadcom Corporation

Inventor： Shom Surendran Ponoth ,  Changyok Park ,  Guang-Jye Shiau ,  Akira Ito

IPC: H01L49/02 ,  H01L27/08 ,  H01L27/108 ,  H01L23/522 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H01L23/5223 ,  H01L27/0805 ,  H01L27/10855 ,  H01L28/40 ,  H01L28/60 ,  H01L28/90 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor structure in a semiconductor device includes a semiconductor substrate having a top surface and a bottom surface opposite the top surface, an isolation region having a top surface and a bottom surface, opposite the top surface, the bottom surface of the isolation region being disposed on the top surface of the semiconductor substrate. The capacitor structure also includes a gate terminal structure disposed on the top surface of the isolation region and a diffusion contact structure disposed on the top surface of the isolation region and arranged parallel to the gate terminal structure. In some aspects, the gate terminal structure is connected to a first contact node and the diffusion contact structure is connected to a second contact node, in which the first and second contact nodes form opposing nodes of the capacitor structure.

Abstract translation: 半导体器件中的电容器结构包括具有顶表面和与顶表面相对的底表面的半导体衬底，隔离区域具有与顶表面相对的顶表面和底表面，隔离区域的底表面设置 在半导体衬底的顶表面上。 电容器结构还包括设置在隔离区域的顶表面上的栅极端子结构和设置在隔离区域的顶表面上且平行于栅极端子结构设置的扩散接触结构。 在一些方面，栅极端子结构连接到第一接触节点，并且扩散接触结构连接到第二接触节点，其中第一和第二接触节点形成电容器结构的相对节点。

公开(公告)号：US09165936B2

公开(公告)日：2015-10-20

申请号：US14173744

申请日：2014-02-05

Applicant: BROADCOM CORPORATION

Inventor： Shom Surendran Ponoth ,  Akira Ito ,  Changyok Park

IPC: H01L29/00 ,  H01L27/112 ,  H01L29/78 ,  H01L29/66 ,  H01L23/525

CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L23/5252 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An anti-fuse device for fin field-effect transistor (finFET) technology includes a dummy gate, an electrically conductive contact, and a diffusion contact. The dummy gate is formed over an end-corner of a fin. The electrically conductive contact is disposed on a portion of the dummy gate and can be used as a first electrode of the device. The diffusion contact is disposed over the fin and can be used as a second electrode of the device.

Abstract translation: 用于鳍状场效应晶体管（finFET）技术的反熔丝器件包括虚拟栅极，导电触点和扩散接触。 虚拟门形成在翅片的端角上。 导电触点设置在虚拟栅极的一部分上，并且可以用作该器件的第一电极。 扩散接触件设置在翅片上并且可以用作该器件的第二电极。

公开(公告)号：US20150097220A1

公开(公告)日：2015-04-09

申请号：US14069174

申请日：2013-10-31

Applicant: BROADCOM CORPORATION

Inventor： Shom Surendran PONOTH ,  Changyok Park ,  Akira Ito

IPC: H01L27/06

CPC classification number: H01L27/0629

Abstract: A fin-shaped field-effect transistor device is provided. The fin-shaped field effect transistor device may include a semiconductor substrate having a top and a bottom surface. The fin-shaped field effect transistor device may also include a fin structure disposed on the top surface of the semiconductor substrate, where the fin structure includes a first sidewall and a second sidewall opposite of the first sidewall. The first sidewall is adjacent to a first region of the top surface of the semiconductor substrate and the second sidewall is adjacent to a second region of the top surface of the semiconductor substrate. The fin-shaped field effect transistor device may also include an insulation layer disposed above the fin structure and the first and second regions of the top surface. The fin-shaped field effect transistor device may also include a conductor structure disposed above and adjacent to the insulation layer.

Abstract translation: 提供了一种鳍状场效应晶体管器件。 鳍状场效应晶体管器件可以包括具有顶表面和底表面的半导体衬底。 鳍状场效应晶体管器件还可以包括设置在半导体衬底的顶表面上的翅片结构，其中鳍结构包括第一侧壁和与第一侧壁相对的第二侧壁。 第一侧壁与半导体衬底的顶表面的第一区相邻，第二侧壁与半导体衬底的顶表面的第二区相邻。 鳍状场效应晶体管器件还可以包括设置在鳍结构上方的绝缘层和顶表面的第一和第二区域。 鳍状场效应晶体管器件还可以包括设置在绝缘层上方并与绝缘层相邻的导体结构。