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    Enabling bulk FINFET-based devices for FINFET technology with dielectric isolation
    2.
    发明授权
    Enabling bulk FINFET-based devices for FINFET technology with dielectric isolation 有权
    使用具有绝缘隔离的FINFET技术的批量FINFET器件

    公开(公告)号：US09209202B2

    公开(公告)日：2015-12-08

    申请号：US14192798

    申请日：2014-02-27

    Applicant: BROADCOM CORPORATION

    Inventor： Shom Surendran Ponoth ,  Changyok Park

    IPC: H01L21/84 ,  H01L27/12 ,  H01L21/762

    CPC classification number: H01L27/1207 ,  H01L21/76224 ,  H01L21/845 ,  H01L27/1211

    Abstract: A method for forming a dielectric-isolated bulk fin field-effect transistor (finFET) device includes forming a second isolation layer over a first structure including multiple partially exposed fins and horizontal areas including a first isolation layer. The second isolation layer is removed from horizontal areas of a first portion of the first structure. An oxide layer is formed under the fins of the first portion of the first structure. The second isolation layer is removed in order to expose the partially exposed fins and horizontal areas of the first structure to form a second structure, on which gate regions are formed.

    Abstract translation: 一种用于形成介质隔离体鳍片场效应晶体管（finFET）器件的方法包括在包括多个部分暴露的鳍片和包括第一隔离层的水平区域的第一结构上形成第二隔离层。 第二隔离层从第一结构的第一部分的水平区域移除。 在第一结构的第一部分的翅片下方形成氧化物层。 去除第二隔离层以暴露第一结构的部分暴露的翅片和水平区域以形成其上形成有栅极区域的第二结构。

    Fin-shaped field effect transistor and capacitor structures
    4.
    发明授权
    Fin-shaped field effect transistor and capacitor structures 有权

    公开(公告)号：US09941271B2

    公开(公告)日：2018-04-10

    申请号：US14069174

    申请日：2013-10-31

    Applicant: BROADCOM CORPORATION

    Inventor： Shom Surendran Ponoth ,  Changyok Park ,  Akira Ito

    IPC: H01L27/10 ,  H01L21/70 ,  H01L27/088 ,  H01L27/06

    CPC classification number: H01L27/0629

    Abstract: A fin-shaped field-effect transistor device is provided. The fin-shaped field effect transistor device may include a semiconductor substrate having a top and a bottom surface. The fin-shaped field effect transistor device may also include a fin structure disposed on the top surface of the semiconductor substrate, where the fin structure includes a first sidewall and a second sidewall opposite of the first sidewall. The first sidewall is adjacent to a first region of the top surface of the semiconductor substrate and the second sidewall is adjacent to a second region of the top surface of the semiconductor substrate. The fin-shaped field effect transistor device may also include an insulation layer disposed above the fin structure and the first and second regions of the top surface. The fin-shaped field effect transistor device may also include a conductor structure disposed above and adjacent to the insulation layer.

    LDMOS device and structure for bulk FinFET technology
    5.
    发明授权
    LDMOS device and structure for bulk FinFET technology 有权
    LDMOS器件和散装FinFET技术的结构

    公开(公告)号：US09379236B2

    公开(公告)日：2016-06-28

    申请号：US14309843

    申请日：2014-06-19

    Applicant: BROADCOM CORPORATION

    Inventor： Shom Surendran Ponoth ,  Akira Ito

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/0886 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7835 ,  H01L29/7851

    Abstract: A lateral double-diffused MOS (LDMOS) bulk finFET device for high-voltage operation includes a first-well region and two or more second-well regions formed on a substrate material and one or more non-well regions including substrate material. The non-well regions are configured to separate well regions of the second-well regions. A source structure is disposed on a first fin that is partially formed on the first-well region. A drain structure is disposed on a second fin that is formed on a last one of the second-well regions. One or more dummy regions are formed on the one or more non-well regions. The dummy regions are configured to provide additional depletion region flow paths including vertical flow paths for charge carriers to enable the high-voltage operation.

    Abstract translation: 用于高电压操作的横向双扩散MOS（LDMOS）体鳍鳍FETFET器件包括形成在衬底材料上的第一阱区域和两个或更多个第二阱区域以及包括衬底材料的一个或多个非阱区域。 非阱区域被配置为分离第二阱区域的阱区域。 源结构设置在部分地形成在第一阱区上的第一鳍上。 漏极结构设置在形成在第二阱区域的最后一个上的第二鳍片上。 在一个或多个非阱区域上形成一个或多个虚拟区域。 虚拟区域被配置为提供额外的耗尽区域流动路径，包括用于电荷载体的垂直流动路径以实现高电压操作。

    ENABLING BULK FINFET-BASED DEVICES FOR FINFET TECHNOLOGY WITH DIELECTRIC ISOLATION
    7.
    发明申请
    ENABLING BULK FINFET-BASED DEVICES FOR FINFET TECHNOLOGY WITH DIELECTRIC ISOLATION 有权
    使用基于FinFET的FinFET技术的电介质隔离器件

    公开(公告)号：US20150228668A1

    公开(公告)日：2015-08-13

    申请号：US14192798

    申请日：2014-02-27

    Applicant: BROADCOM CORPORATION

    Inventor： Shom Surendran Ponoth ,  Changyok Park

    IPC: H01L27/12 ,  H01L21/762

    CPC classification number: H01L27/1207 ,  H01L21/76224 ,  H01L21/845 ,  H01L27/1211

    Abstract: A method for forming a dielectric-isolated bulk fin field-effect transistor (finFET) device includes forming a second isolation layer over a first structure including multiple partially exposed fins and horizontal areas including a first isolation layer. The second isolation layer is removed from horizontal areas of a first portion of the first structure. An oxide layer is formed under the fins of the first portion of the first structure. The second isolation layer is removed in order to expose the partially exposed fins and horizontal areas of the first structure to form a second structure, on which gate regions are formed.

    Abstract translation: 一种用于形成介质隔离体鳍片场效应晶体管（finFET）器件的方法包括在包括多个部分暴露的鳍片和包括第一隔离层的水平区域的第一结构上形成第二隔离层。 第二隔离层从第一结构的第一部分的水平区域移除。 在第一结构的第一部分的翅片下方形成氧化物层。 去除第二隔离层以暴露第一结构的部分暴露的翅片和水平区域以形成其上形成有栅极区域的第二结构。

    Metal-insulator-metal capacitor structure
    8.
    发明授权
    Metal-insulator-metal capacitor structure 有权
    金属 - 绝缘体 - 金属电容器结构

    公开(公告)号：US09337188B2

    公开(公告)日：2016-05-10

    申请号：US14072723

    申请日：2013-11-05

    Applicant: Broadcom Corporation

    Inventor： Shom Surendran Ponoth ,  Changyok Park ,  Guang-Jye Shiau ,  Akira Ito

    IPC: H01L49/02 ,  H01L27/08 ,  H01L27/108 ,  H01L23/522 ,  H01L27/06

    CPC classification number: H01L27/0629 ,  H01L23/5223 ,  H01L27/0805 ,  H01L27/10855 ,  H01L28/40 ,  H01L28/60 ,  H01L28/90 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A capacitor structure in a semiconductor device includes a semiconductor substrate having a top surface and a bottom surface opposite the top surface, an isolation region having a top surface and a bottom surface, opposite the top surface, the bottom surface of the isolation region being disposed on the top surface of the semiconductor substrate. The capacitor structure also includes a gate terminal structure disposed on the top surface of the isolation region and a diffusion contact structure disposed on the top surface of the isolation region and arranged parallel to the gate terminal structure. In some aspects, the gate terminal structure is connected to a first contact node and the diffusion contact structure is connected to a second contact node, in which the first and second contact nodes form opposing nodes of the capacitor structure.

    Abstract translation: 半导体器件中的电容器结构包括具有顶表面和与顶表面相对的底表面的半导体衬底，隔离区域具有与顶表面相对的顶表面和底表面，隔离区域的底表面设置 在半导体衬底的顶表面上。 电容器结构还包括设置在隔离区域的顶表面上的栅极端子结构和设置在隔离区域的顶表面上且平行于栅极端子结构设置的扩散接触结构。 在一些方面，栅极端子结构连接到第一接触节点，并且扩散接触结构连接到第二接触节点，其中第一和第二接触节点形成电容器结构的相对节点。

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