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    SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device
    2.
    发明授权
    SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device 有权
    基于SOI的场效应晶体管在通道下方的底切区域具有压缩膜，以及制造该器件的方法

    公开(公告)号：US06717216B1

    公开(公告)日：2004-04-06

    申请号：US10318601

    申请日：2002-12-12

    申请人： Bruce B. Doris ,  Dureseti Chidambarrao ,  Xavier Baie ,  Jack A. Mandelman ,  Devendra K. Sadana ,  Dominic J. Schepis

    发明人： Bruce B. Doris ,  Dureseti Chidambarrao ,  Xavier Baie ,  Jack A. Mandelman ,  Devendra K. Sadana ,  Dominic J. Schepis

    IPC分类号： H01L2701

    CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78696

    摘要： Field effect transistor with increased charge carrier mobility due to stress in the current channel 22. The stress is in the direction of current flow (longitudinal). In PFET devices, the stress is compressive; in NFET devices, the stress is tensile. The stress is created by a compressive film 34 in an area 32 under the channel. The compressive film pushes up on the channel 22, causing it to bend. In PFET devices, the compressive film is disposed under ends 31 of the channel (e.g. under the source and drain), thereby causing compression in an upper portion 22A of the channel. In NFET devices, the compressive film is disposed under a middle portion 40 of the channel (e.g. under the gate), thereby causing tension in the, upper portion of the channel. Therefore, both NFET and PFET devices can be enhanced. A method for making the devices is included.

    摘要翻译： 场效应晶体管由于电流通道22中的应力而具有增加的电荷载流子迁移率。应力在电流方向（纵向）。 在PFET器件中，应力是压缩的; 在NFET器件中，应力为拉伸。 应力由通道下的区域32中的压缩膜34产生。 压缩膜在通道22上向上推动，使其弯曲。 在PFET器件中，压缩膜设置在通道的端部31（例如在源极和漏极下），从而在通道的上部22A中引起压缩。 在NFET器件中，压缩膜设置在通道的中间部分40（例如在栅极下），从而在通道的上部产生张力。 因此，可以增强NFET和PFET器件。 包括制造装置的方法。

    Stress inducing spacers
    3.
    发明授权
    Stress inducing spacers 有权
    应力诱导垫片

    公开(公告)号：US07374987B2

    公开(公告)日：2008-05-20

    申请号：US10935136

    申请日：2004-09-07

    申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce B. Doris ,  Jack A. Mandelman ,  Xavier Baie

    发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce B. Doris ,  Jack A. Mandelman ,  Xavier Baie

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42316 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/808

    摘要： A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.

    摘要翻译： 在张力和/或压缩下的基底改善了在其中制造的器件的性能。 可以通过选择设置在器件沟道区域上方的适当的栅极侧壁间隔物施加张力和/或压缩，其中间隔物邻近栅极和衬底形成，并且在邻近衬底区域上施加力。 另一个实施例包括使用通过氧化扩展的多晶硅制成的SOI侧壁间隔施加在沟道的平面中的压应力。 在压缩或张力下的衬底区域表现出不同于非应力衬底的电荷迁移率特性。 通过可控地改变在衬底上形成的NFET和PFET器件内的这些应力，已经证明了IC性能的提高。

    Stress inducing spacers
    4.
    发明授权
    Stress inducing spacers 有权
    应力诱导垫片

    公开(公告)号：US06825529B2

    公开(公告)日：2004-11-30

    申请号：US10318602

    申请日：2002-12-12

    申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce B. Doris ,  Jack A. Mandelman ,  Xavier Baie

    发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce B. Doris ,  Jack A. Mandelman ,  Xavier Baie

    IPC分类号： H01L2976

    CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42316 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/808

    摘要： A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.

    摘要翻译： 在张力和/或压缩下的基底改善了在其中制造的器件的性能。 可以通过选择设置在器件沟道区域上方的适当的栅极侧壁间隔物施加张力和/或压缩，其中间隔物邻近栅极和衬底形成，并且在邻近衬底区域上施加力。 另一个实施例包括使用通过氧化扩展的多晶硅制成的SOI侧壁间隔施加在沟道的平面中的压应力。 在压缩或张力下的衬底区域表现出不同于非应力衬底的电荷迁移率特性。 通过可控地改变在衬底上形成的NFET和PFET器件内的这些应力，已经证明了IC性能的提高。

    Strained finFET CMOS device structures
    6.
    发明授权
    Strained finFET CMOS device structures 有权
    应变finFET CMOS器件结构

    公开(公告)号：US07388259B2

    公开(公告)日：2008-06-17

    申请号：US10536483

    申请日：2002-11-25

    申请人： Bruce B. Doris ,  Dureseti Chidambarrao ,  MeiKei Ieong ,  Jack A. Mandelman

    发明人： Bruce B. Doris ,  Dureseti Chidambarrao ,  MeiKei Ieong ,  Jack A. Mandelman

    IPC分类号： H01L29/94

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/7843 ,  H01L29/785

    摘要： A semiconductor device structure, includes a PMOS device 200 and an NMOS device 300 disposed on a substrate 1,2, the PMOS device including a compressive layer 6 stressing an active region of the PMOS device, the NMOS device including a tensile layer 9 stressing an active region of the NMOS device, wherein the compressive layer includes a first dielectric material, the tensile layer includes a second dielectric material, and the PMOS and NMOS devices are FinFET devices 200, 300.

    摘要翻译： 半导体器件结构包括PMOS器件200和设置在衬底1,2上的NMOS器件300，PMOS器件包括压迫PMOS器件的有源区的压缩层6，NMOS器件包括拉伸层9， 所述NMOS器件的有源区，其中所述压缩层包括第一介电材料，所述拉伸层包括第二介电材料，并且所述PMOS和NMOS器件为FinFET器件200,300。

    Silicon-on-insulator vertical array device trench capacitor DRAM
    7.
    发明授权
    Silicon-on-insulator vertical array device trench capacitor DRAM 有权
    绝缘体上的垂直阵列器件沟槽电容器DRAM

    公开(公告)号：US06566177B1

    公开(公告)日：2003-05-20

    申请号：US09427257

    申请日：1999-10-25

    申请人： Carl J. Radens ,  Gary B. Bronner ,  Tze-chiang Chen ,  Bijan Davari ,  Jack A. Mandelman ,  Dan Moy ,  Devendra K. Sadana ,  Ghavam Ghavami Shahidi ,  Scott R. Stiffler

    发明人： Carl J. Radens ,  Gary B. Bronner ,  Tze-chiang Chen ,  Bijan Davari ,  Jack A. Mandelman ,  Dan Moy ,  Devendra K. Sadana ,  Ghavam Ghavami Shahidi ,  Scott R. Stiffler

    IPC分类号： H01L2100

    CPC分类号： H01L27/10864 ,  H01L27/1087

    摘要： A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer isolates an SOI layer from a silicon substrate. The trench capacitor is formed in the substrate and the access transistor is formed on a sidewall of the SOI layer. A polysilicon strap connected to the polysilicon plate of the storage capacitor provides a self-aligned contact to the source of the access transistor. Initially, the buried oxide layer is formed in the wafer. Deep trenches are etched, initially just through the SOI layer and the BOX layer. Protective sidewalls are formed in the trenches. Then, the deep trenches are etched into the substrate. The volume in the substrate is expanded to form a bottle shaped trench. A polysilicon capacitor plate is formed in the deep trenches and conductive polysilicon straps are formed in the trenches between the capacitor plates and the SOI sidewalls. Device regions are defined in the wafer and a sidewall gate is formed in the deep trenches. Shallow trenches isolation (STI) is used to isolate and define cells. Bitlines and wordlines are formed on the wafer.

    摘要翻译： 一种绝缘体上硅（SOI）动态随机存取存储器（DRAM）单元及阵列及其制造方法。 存储单元包括通过自对准埋入带连接到垂直存取晶体管的沟槽存储电容器。 掩埋氧化层将SOI层与硅衬底隔离。 沟槽电容器形成在衬底中，并且存取晶体管形成在SOI层的侧壁上。 连接到存储电容器的多晶硅板的多晶硅带提供与存取晶体管的源极的自对准接触。 最初，在晶圆中形成掩埋氧化物层。 深沟槽被蚀刻，最初刚刚通过SOI层和BOX层。 在沟槽中形成保护侧壁。 然后，将深沟槽蚀刻到衬底中。 衬底中的体积被扩大以形成瓶形沟槽。 在深沟槽中形成多晶硅电容器板，并且在电容器板和SOI侧壁之间的沟槽中形成导电多晶硅带。 在晶片中限定器件区域，并且在深沟槽中形成侧壁栅极。 浅沟槽隔离（STI）用于隔离和定义细胞。 在晶片上形成位线和字线。

    Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap
    8.
    发明授权
    Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap 失效
    绝缘体上的垂直阵列DRAM单元，具有自对准埋地带

    公开(公告)号：US06426252B1

    公开(公告)日：2002-07-30

    申请号：US09427256

    申请日：1999-10-25

    申请人： Carl J. Radens ,  Gary B. Bronner ,  Tze-chiang Chen ,  Bijan Davari ,  Jack A. Mandelman ,  Dan Moy ,  Devendra K. Sadana ,  Ghavam Ghavami Shahidi ,  Scott R. Stiffler

    发明人： Carl J. Radens ,  Gary B. Bronner ,  Tze-chiang Chen ,  Bijan Davari ,  Jack A. Mandelman ,  Dan Moy ,  Devendra K. Sadana ,  Ghavam Ghavami Shahidi ,  Scott R. Stiffler

    IPC分类号： H01L218242

    CPC分类号： H01L27/10864 ,  H01L27/10867 ,  H01L27/1203

    摘要： A silicon on insulator (SOI) dynamic random access memory (DRAM) cell, array and method of manufacture. The memory cell includes a vertical access transistor above a trench storage capacitor in a layered wafer. A buried oxide (BOX) layer formed in a silicon wafer isolates an SOI layer from a silicon substrate. Deep trenches are etched through the upper surface SOI layer, the BOX layer and into the substrate. Each trench capacitor is formed in the substrate and, the access transistor is formed on a sidewall of the SOI layer. Recesses are formed in the BOX layer at the SOI layer. A polysilicon strap recessed in the BOX layer connects each polysilicon storage capacitor plate to a self-aligned contact at the source of the access transistor. Dopant is implanted into the wafer to define device regions. Access transistor gates are formed along the SOI layer sidewalls. Shallow trenches are formed and filled with insulating material to isolate cells from adjacent cells. Wordlines and bitlines are formed to complete the memory array.

    摘要翻译： 绝缘体上硅（SOI）动态随机存取存储器（DRAM）单元，阵列和制造方法。 存储单元包括在分层晶片中的沟槽存储电容器上方的垂直存取晶体管。 形成在硅晶片中的掩埋氧化物（BOX）层将SOI层与硅衬底隔离。 深沟槽通过上表面SOI层，BOX层蚀刻并进入衬底。 每个沟槽电容器形成在衬底中，并且存取晶体管形成在SOI层的侧壁上。 在SOI层的BOX层中形成凹部。 凹陷在BOX层中的多晶硅带将每个多晶硅存储电容器板连接到存取晶体管的源极处的自对准接触。 将掺杂剂注入到晶片中以限定器件区域。 存取晶体管栅极沿SOI层侧壁形成。 形成浅沟槽并填充绝缘材料以将细胞与相邻细胞分离。 形成字词和位线以完成内存数组。

    Vertical DRAM punchthrough stop self-aligned to storage trench
    10.
    发明授权
    Vertical DRAM punchthrough stop self-aligned to storage trench 有权
    垂直DRAM穿透停止自对准到存储沟槽

    公开(公告)号：US06777737B2

    公开(公告)日：2004-08-17

    申请号：US10016605

    申请日：2001-10-30

    申请人： Jack A. Mandelman ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni

    发明人： Jack A. Mandelman ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni

    IPC分类号： H01L27108

    CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10885 ,  H01L29/66181 ,  H01L29/945

    摘要： A semiconductor memory structure having a feature size of less than about 90 nm which exhibits little or no dynamic charge loss and little or no trap assisted junction leakage is provided. Specifically, the semiconductor structure includes at least one back-to-back pair of trench storage memory cells present in a Si-containing substrate. Each memory cell includes a vertical transistor overlaying a trench capacitor. Strap outdiffusions are present on each vertical sidewall of the trench storage memory cells so as to interconnect the vertical transistor and the trench capacitor of each memory cell to the Si-containing substrate. A punchthrough stop doping pocket is located between each back-to-back pair of trench storage memory cells and it is centered between the strap outdiffusions of adjacent storage trenches, and self-aligned to the adjacent storage trenches.

    摘要翻译： 具有小于约90nm的特征尺寸的显示器很少或没有动态电荷损失并且很少或没有陷阱辅助结漏电的半导体存储器结构被提供。 具体地，半导体结构包括存在于含Si衬底中的至少一个背靠背对的沟槽存储存储单元。 每个存储单元包括覆盖沟槽电容器的垂直晶体管。 在沟槽存储单元的每个垂直侧壁上都存在带外扩散，以将每个存储单元的垂直晶体管和沟槽电容器互连到含Si衬底。 穿通阻止掺杂袋位于每个背对背对的沟槽存储存储单元之间，并且其位于相邻存储沟槽的带外扩展之间并且与相邻存储沟槽自对准。