公开(公告)号：US06884667B1

公开(公告)日：2005-04-26

申请号：US10669727

申请日：2003-09-25

申请人： Bruce B. Doris ,  Dureseti Chidambarrao ,  Xavier Baie ,  Jack A. Mandelman ,  Devendra K. Sadana ,  Dominic J. Schepis

发明人： Bruce B. Doris ,  Dureseti Chidambarrao ,  Xavier Baie ,  Jack A. Mandelman ,  Devendra K. Sadana ,  Dominic J. Schepis

IPC分类号： H01L27/08 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L21/00

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78696

摘要： Field effect transistor with increased charge carrier mobility due to stress in the current channel 22. The stress is in the direction of current flow (longitudinal). In PFET device, the stress is compressive; in NFET devices, the stress is tensile. The stress is created by a compressive film 34 in an area 32 under the channel. The compressive film pushes up on the channel 22, causing it to bend. In PFET devices, the compressive film is disposed under ends 31 of the channel (e.g. under the source and drain), thereby causing compression in an upper portion 22A of the channel. In NFET devices, the compressive film is disposed under a middle portion 40 of the channel (e.g. under the gate), thereby causing tension in the, upper portion of the channel. Therefore, both NFET and PFET device can be enhanced. A method for making the devices is included.

摘要翻译： 场效应晶体管由于电流通道22中的应力而具有增加的电荷载流子迁移率。 应力在电流方向（纵向）。 在PFET器件中，应力是压缩的; 在NFET器件中，应力为拉伸。 应力由通道下的区域32中的压缩膜34产生。 压缩膜在通道22上向上推动，使其弯曲。 在PFET器件中，压缩膜设置在通道的端部31（例如在源极和漏极之下），从而在通道的上部22A中引起压缩。 在NFET器件中，压缩膜设置在通道的中间部分40（例如在栅极下），从而在通道的上部产生张力。 因此，可以增强NFET和PFET器件。 包括制造装置的方法。

公开(公告)号：US06717216B1

公开(公告)日：2004-04-06

申请号：US10318601

申请日：2002-12-12

申请人： Bruce B. Doris ,  Dureseti Chidambarrao ,  Xavier Baie ,  Jack A. Mandelman ,  Devendra K. Sadana ,  Dominic J. Schepis

发明人： Bruce B. Doris ,  Dureseti Chidambarrao ,  Xavier Baie ,  Jack A. Mandelman ,  Devendra K. Sadana ,  Dominic J. Schepis

IPC分类号： H01L2701

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78696

摘要： Field effect transistor with increased charge carrier mobility due to stress in the current channel 22. The stress is in the direction of current flow (longitudinal). In PFET devices, the stress is compressive; in NFET devices, the stress is tensile. The stress is created by a compressive film 34 in an area 32 under the channel. The compressive film pushes up on the channel 22, causing it to bend. In PFET devices, the compressive film is disposed under ends 31 of the channel (e.g. under the source and drain), thereby causing compression in an upper portion 22A of the channel. In NFET devices, the compressive film is disposed under a middle portion 40 of the channel (e.g. under the gate), thereby causing tension in the, upper portion of the channel. Therefore, both NFET and PFET devices can be enhanced. A method for making the devices is included.

摘要翻译： 场效应晶体管由于电流通道22中的应力而具有增加的电荷载流子迁移率。应力在电流方向（纵向）。 在PFET器件中，应力是压缩的; 在NFET器件中，应力为拉伸。 应力由通道下的区域32中的压缩膜34产生。 压缩膜在通道22上向上推动，使其弯曲。 在PFET器件中，压缩膜设置在通道的端部31（例如在源极和漏极下），从而在通道的上部22A中引起压缩。 在NFET器件中，压缩膜设置在通道的中间部分40（例如在栅极下），从而在通道的上部产生张力。 因此，可以增强NFET和PFET器件。 包括制造装置的方法。

公开(公告)号：US07374987B2

公开(公告)日：2008-05-20

申请号：US10935136

申请日：2004-09-07

申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce B. Doris ,  Jack A. Mandelman ,  Xavier Baie

发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce B. Doris ,  Jack A. Mandelman ,  Xavier Baie

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42316 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/808

摘要： A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.

摘要翻译： 在张力和/或压缩下的基底改善了在其中制造的器件的性能。 可以通过选择设置在器件沟道区域上方的适当的栅极侧壁间隔物施加张力和/或压缩，其中间隔物邻近栅极和衬底形成，并且在邻近衬底区域上施加力。 另一个实施例包括使用通过氧化扩展的多晶硅制成的SOI侧壁间隔施加在沟道的平面中的压应力。 在压缩或张力下的衬底区域表现出不同于非应力衬底的电荷迁移率特性。 通过可控地改变在衬底上形成的NFET和PFET器件内的这些应力，已经证明了IC性能的提高。

公开(公告)号：US06825529B2

公开(公告)日：2004-11-30

申请号：US10318602

申请日：2002-12-12

申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce B. Doris ,  Jack A. Mandelman ,  Xavier Baie

发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce B. Doris ,  Jack A. Mandelman ,  Xavier Baie

IPC分类号： H01L2976

CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42316 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/808

摘要： A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.

摘要翻译： 在张力和/或压缩下的基底改善了在其中制造的器件的性能。 可以通过选择设置在器件沟道区域上方的适当的栅极侧壁间隔物施加张力和/或压缩，其中间隔物邻近栅极和衬底形成，并且在邻近衬底区域上施加力。 另一个实施例包括使用通过氧化扩展的多晶硅制成的SOI侧壁间隔施加在沟道的平面中的压应力。 在压缩或张力下的衬底区域表现出不同于非应力衬底的电荷迁移率特性。 通过可控地改变在衬底上形成的NFET和PFET器件内的这些应力，已经证明了IC性能的提高。

公开(公告)号：US20050040460A1

公开(公告)日：2005-02-24

申请号：US10935136

申请日：2004-09-07

申请人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Bruce Doris ,  Jack Mandelman ,  Xavier Baie

发明人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Bruce Doris ,  Jack Mandelman ,  Xavier Baie

IPC分类号： H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/808 ,  H03B1/00 ,  H01L29/76 ,  H03K3/00

CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42316 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/808

摘要： A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.

摘要翻译： 在张力和/或压缩下的基底改善了在其中制造的器件的性能。 可以通过选择设置在器件沟道区域上方的适当的栅极侧壁间隔物施加张力和/或压缩，其中间隔物邻近栅极和衬底形成，并且在邻近衬底区域上施加力。 另一个实施例包括使用通过氧化扩展的多晶硅制成的SOI侧壁间隔施加在沟道的平面中的压应力。 在压缩或张力下的衬底区域表现出不同于非应力衬底的电荷迁移率特性。 通过可控地改变在衬底上形成的NFET和PFET器件内的这些应力，已经证明了IC性能的提高。

公开(公告)号：US06624478B2

公开(公告)日：2003-09-23

申请号：US09683656

申请日：2002-01-30

申请人： Brent A. Anderson ,  Xavier Baie ,  Randy W. Mann ,  Edward J. Nowak ,  Jed H. Rankin

发明人： Brent A. Anderson ,  Xavier Baie ,  Randy W. Mann ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L2701

CPC分类号： H01L29/7842 ,  H01L21/84 ,  H01L27/1203

摘要： The present invention provides a device design and method for forming Field Effect Transistors (FETs) that have improved performance without negative impacts to device density. The present invention forms high-gain p-channel transistors by forming them on silicon islands where hole mobility has been increased. The hole mobility is increased by applying physical straining to the silicon islands. By straining the silicon islands, the hole mobility is increased resulting in increased device gain. This is accomplished without requiring an increase in the size of the devices, or the size of the contacts to the devices.

摘要翻译： 本发明提供了一种用于形成场效应晶体管（FET）的器件设计和方法，其具有改进的性能而不会对器件密度造成负面影响。 本发明通过在硅岛上形成高增益p沟道晶体管，其中空穴迁移率已经增加。 通过对硅岛施加物理应变来增加空穴迁移率。 通过拉伸硅岛，空穴迁移率增加，导致器件增益增加。 这是在不需要增加设备尺寸或者与设备的触点的尺寸的情况下实现的。

公开(公告)号：US06962838B2

公开(公告)日：2005-11-08

申请号：US10447579

申请日：2003-05-29

申请人： Brent A. Anderson ,  Xavier Baie ,  Randy W. Mann ,  Edward J. Nowak ,  Jed H. Rankin

发明人： Brent A. Anderson ,  Xavier Baie ,  Randy W. Mann ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L21/00

CPC分类号： H01L29/7842 ,  H01L21/84 ,  H01L27/1203

摘要： The present invention provides a device design and method for forming Field Effect Transistors (FETs) that have improved performance without negative impacts to device density. The present invention forms high-gain p-channel transistors by forming them on silicon islands where hole mobility has been increased. The hole mobility is increased by applying physical straining to the silicon islands. By straining the silicon islands, the hole mobility is increased resulting in increased device gain. This is accomplished without requiring an increase in the size of the devices, or the size of the contacts to the devices.

摘要翻译： 本发明提供了一种用于形成场效应晶体管（FET）的器件设计和方法，其具有改进的性能而不会对器件密度造成负面影响。 本发明通过在硅岛上形成高增益p沟道晶体管，其中空穴迁移率已经增加。 通过对硅岛施加物理应变来增加空穴迁移率。 通过拉伸硅岛，空穴迁移率增加，导致器件增益增加。 这是在不需要增加设备尺寸或者与设备的触点的尺寸的情况下实现的。