公开(公告)号：US20050237786A1

公开(公告)日：2005-10-27

申请号：US11155780

申请日：2005-06-20

申请人： Bryan Atwood ,  Kazuo Yano ,  Tomoyuki Ishii ,  Taro Osabe ,  Kazumasa Yanagisawa ,  Takeshi Sakata

发明人： Bryan Atwood ,  Kazuo Yano ,  Tomoyuki Ishii ,  Taro Osabe ,  Kazumasa Yanagisawa ,  Takeshi Sakata

IPC分类号： G11C11/00 ,  G11C11/401 ,  G11C11/405 ,  G11C11/406 ,  G11C11/4076 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  H01L27/12

CPC分类号： H01L27/105 ,  G11C11/405 ,  G11C11/406 ,  G11C11/4076 ,  G11C2207/2281 ,  G11C2207/229 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/1203

摘要： A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that cell size of two-and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.

摘要翻译： 本发明提供了高集成度的动态随机存取存储器。 此外，提供了一种写入方法，使得减小了二晶体管和三晶体管增益单元存储器的单元尺寸。 一种结合了作为写入元件的薄沟道晶体管的动态存储器，使得在本发明的存储器件中实现长的数据存储保持。 通过本发明也实现了具有低操作功率和高密度的动态存储单元。

公开(公告)号：US06787835B2

公开(公告)日：2004-09-07

申请号：US10167754

申请日：2002-06-11

申请人： Bryan Atwood ,  Kazuo Yano ,  Tomoyuki Ishii ,  Taro Osabe ,  Kazumasa Yanagisawa ,  Takeshi Sakata

发明人： Bryan Atwood ,  Kazuo Yano ,  Tomoyuki Ishii ,  Taro Osabe ,  Kazumasa Yanagisawa ,  Takeshi Sakata

IPC分类号： H01L27108

CPC分类号： H01L27/105 ,  G11C11/405 ,  G11C11/406 ,  G11C11/4076 ,  G11C2207/2281 ,  G11C2207/229 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/1203

摘要： A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that the cell size of two- and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.

摘要翻译： 本发明提供了高集成度的动态随机存取存储器。 此外，提供了一种写入方法，使得减少了双晶体管和三晶体管增益单元存储器的单元尺寸。 一种结合了作为写入元件的薄沟道晶体管的动态存储器，使得在本发明的存储器件中实现长的数据存储保持。 通过本发明也实现了具有低操作功率和高密度的动态存储单元。

公开(公告)号：US06949782B2

公开(公告)日：2005-09-27

申请号：US10790183

申请日：2004-03-02

申请人： Bryan Atwood ,  Kazuo Yano ,  Tomoyuki Ishii ,  Taro Osabe ,  Kazumasa Yanagisawa ,  Takeshi Sakata

发明人： Bryan Atwood ,  Kazuo Yano ,  Tomoyuki Ishii ,  Taro Osabe ,  Kazumasa Yanagisawa ,  Takeshi Sakata

IPC分类号： G11C11/00 ,  G11C11/401 ,  G11C11/405 ,  G11C11/406 ,  G11C11/4076 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  H01L27/12

CPC分类号： H01L27/105 ,  G11C11/405 ,  G11C11/406 ,  G11C11/4076 ,  G11C2207/2281 ,  G11C2207/229 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/1203

摘要： A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that the cell size of two-and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.

摘要翻译： 本发明提供了高集成度的动态随机存取存储器。 此外，提供了一种写入方法，使得减少了二晶体管和三晶体管增益单元存储器的单元尺寸。 一种结合了作为写入元件的薄沟道晶体管的动态存储器，使得在本发明的存储器件中实现长的数据存储保持。 通过本发明也实现了具有低操作功率和高密度的动态存储单元。

公开(公告)号：US20080042193A1

公开(公告)日：2008-02-21

申请号：US11896800

申请日：2007-09-06

申请人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

发明人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

IPC分类号： H01L29/792

CPC分类号： H01L27/11521 ,  B82Y10/00 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/06 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887

摘要： For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

摘要翻译： 为了通过电池级提供具有提高可靠性的便宜的半导体存储器件，以代替通过诸如ECC的电存储器单元中的缺陷脱离，并且还用于提供能够在垂直方向上按比例缩小的单元结构，同时保持 在需要高速读出操作的半导体存储器件中的可靠性，电荷存储区域由大量半导体电荷存储小区域制成的粒子构成，各自独立，从而通过 细胞水平。

公开(公告)号：US06849895B2

公开(公告)日：2005-02-01

申请号：US09944073

申请日：2001-09-04

申请人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

发明人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L27/108

CPC分类号： H01L27/11521 ,  B82Y10/00 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/06 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887

摘要： For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

公开(公告)号：US20110169070A1

公开(公告)日：2011-07-14

申请号：US13072211

申请日：2011-03-25

申请人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

发明人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

IPC分类号： H01L27/088

CPC分类号： H01L27/11521 ,  B82Y10/00 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/06 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887

摘要： For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

摘要翻译： 为了通过电池级提供具有提高可靠性的便宜的半导体存储器件，以代替通过诸如ECC的电存储器单元中的缺陷脱离，并且还用于提供能够在垂直方向上按比例缩小的单元结构，同时保持 在需要高速读出操作的半导体存储器件中的可靠性，电荷存储区域由大量半导体电荷存储小区域制成的粒子构成，各自独立，从而通过 细胞水平。

公开(公告)号：US08278700B2

公开(公告)日：2012-10-02

申请号：US13072211

申请日：2011-03-25

申请人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

发明人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

IPC分类号： H01L29/792

CPC分类号： H01L27/11521 ,  B82Y10/00 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/06 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887

摘要： For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

摘要翻译： 为了通过电池级提供具有提高可靠性的便宜的半导体存储器件，以代替通过诸如ECC的电存储器单元中的缺陷脱离，并且还用于提供能够在垂直方向上按比例缩小的单元结构，同时保持 在需要高速读出操作的半导体存储器件中的可靠性，电荷存储区域由大量半导体电荷存储小区域制成的粒子构成，各自独立，从而通过 细胞水平。

公开(公告)号：US07939879B2

公开(公告)日：2011-05-10

申请号：US11896800

申请日：2007-09-06

申请人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

发明人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

IPC分类号： H01L29/792

CPC分类号： H01L27/11521 ,  B82Y10/00 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/06 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887

摘要： For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

摘要翻译： 为了通过电池级提供具有提高可靠性的便宜的半导体存储器件，以代替通过诸如ECC的电存储器单元中的缺陷脱离，并且还用于提供能够在垂直方向上按比例缩小的单元结构，同时保持 在需要高速读出操作的半导体存储器件中的可靠性，电荷存储区域由大量半导体电荷存储小区域制成的粒子构成，各自独立，从而通过 细胞水平。

公开(公告)号：US07078762B2

公开(公告)日：2006-07-18

申请号：US10883738

申请日：2004-07-06

申请人： Tomoyuki Ishii ,  Taro Osabe ,  Hideaki Kurata ,  Takeshi Sakata

发明人： Tomoyuki Ishii ,  Taro Osabe ,  Hideaki Kurata ,  Takeshi Sakata

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  B82Y10/00 ,  G11C11/5621 ,  G11C11/5671 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0475 ,  G11C16/0491 ,  G11C2216/06 ,  H01L27/115 ,  H01L27/11521

摘要： Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a p-type well through a gate oxide film. In the upper part of an interlayer insulator that covers those assist gates are formed word lines that are used as control electrodes. The width of those word lines is, for example, 0.1 μm, and each word line is separated from its adjacent word lines by a side wall spacer that is a silicon oxide film having a thickness of about 20 nm.

公开(公告)号：US07622766B2

公开(公告)日：2009-11-24

申请号：US11808228

申请日：2007-06-07

申请人： Tomoyuki Ishii ,  Taro Osabe ,  Hideaki Kurata ,  Takeshi Sakata

发明人： Tomoyuki Ishii ,  Taro Osabe ,  Hideaki Kurata ,  Takeshi Sakata

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  B82Y10/00 ,  G11C11/5621 ,  G11C11/5671 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0475 ,  G11C16/0491 ,  G11C2216/06 ,  H01L27/115 ,  H01L27/11521

摘要： Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a p-type well through a gate oxide film. In the upper part of an interlayer insulator that covers those assist gates are formed word lines that are used as control electrodes. The width of those word lines is, for example, 0.1 μm, and each word line is separated from its adjacent word lines by a side wall spacer that is a silicon oxide film having a thickness of about 20 nm.

摘要翻译： 公开了使用设置在半导体衬底上的反转层作为数据线的非易失性半导体存储器件。 存储器件可以减少存储器单元之间的特性变化并且可以降低位成本。 多个辅助栅极通过栅极氧化膜形成在p型阱的上部。 在覆盖这些辅助栅极的层间绝缘体的上部形成用作控制电极的字线。 这些字线的宽度例如为0.1μm，并且每个字线通过作为厚度为约20nm的氧化硅膜的侧壁间隔物与其相邻字线分开。