公开(公告)号：US08703345B2

公开(公告)日：2014-04-22

申请号：US13243178

申请日：2011-09-23

申请人： Byoung-Bae Lee ,  Jae-Seung Oh ,  Sang-Hyun Lee ,  Kwon-Young Choi ,  Dong-Su Kim ,  Yeon-Suk Hong ,  Hyo-Jin Lee

发明人： Byoung-Bae Lee ,  Jae-Seung Oh ,  Sang-Hyun Lee ,  Kwon-Young Choi ,  Dong-Su Kim ,  Yeon-Suk Hong ,  Hyo-Jin Lee

IPC分类号： H01M6/16

CPC分类号： C07C271/00 ,  C07C275/00 ,  H01G11/06 ,  H01G11/56 ,  H01M10/052 ,  H01M10/0565 ,  H01M10/0569 ,  H01M2300/0034 ,  H01M2300/0037 ,  H01M2300/004 ,  H01M2300/0082 ,  H01M2300/0085 ,  Y02E60/13

摘要： Disclosed is an electrolyte. The electrolyte includes an amide compound and an ionizable lithium salt. The amide compound has a specific structure in which an amine group is substituted with at least one alkoxyalkyl group and at least one halogen atom is present. The electrolyte has good thermal and chemical stability, a low resistance and a high ionic conductivity. In addition, the electrolyte has a high upper limit of electrochemical window due to its improved oxidation stability. Therefore, the electrolyte can be useful for the fabrication of an electrochemical device. Further disclosed is an electrochemical device including the electrolyte.

摘要翻译： 公开了电解质。 电解质包括酰胺化合物和可电离的锂盐。 酰胺化合物具有其中胺基被至少一个烷氧基烷基取代并且存在至少一个卤素原子的特定结构。 电解质具有良好的热和化学稳定性，低电阻和高离子电导率。 此外，由于其改善的氧化稳定性，电解质具有高的电化学窗口上限。 因此，电解质可用于制造电化学装置。 还公开了包括电解质的电化学装置。

公开(公告)号：US07659625B2

公开(公告)日：2010-02-09

申请号：US12333973

申请日：2008-12-12

申请人： Seung-Taek Lim ,  Mun-Pyo Hong ,  Nam-Seok Roh ,  Young-Joo Song ,  Sang-Ki Kwak ,  Kwon-Young Choi ,  Keun-Kyu Song

发明人： Seung-Taek Lim ,  Mun-Pyo Hong ,  Nam-Seok Roh ,  Young-Joo Song ,  Sang-Ki Kwak ,  Kwon-Young Choi ,  Keun-Kyu Song

IPC分类号： H01L23/48

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L21/76805 ,  H01L21/76816 ,  H01L23/53223 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads.

摘要翻译： 在制造用于液晶显示器的薄膜晶体管阵列基板的方法中，栅极线组件在沿水平方向前进的基底上形成有铬基底层和基于铝合金的超层。 栅极线组件具有栅极线，栅电极和栅极焊盘。 栅极绝缘层沉积在绝缘基板上，使得栅极绝缘层覆盖栅极线组件。 在栅极绝缘层上依次形成半导体层和欧姆接触层。 数据线组件在欧姆接触层上形成有铬基底层和基于铝合金的超层。 数据线组件具有跨越栅极线，源电极，漏电极和数据焊盘的数据线。 保护层沉积到衬底上，并被图案化，从而形成露出漏电极，栅极焊盘和数据焊盘的接触孔。 用于栅极线组件和数据线组件的下层的侧壁通过接触孔暴露。 将基于IZO的层沉积到衬底上并构图，从而形成像素电极，辅助栅极焊盘和辅助数据焊盘。 像素电极连接到漏电极的侧壁，辅助栅极和数据焊盘连接到栅极和数据焊盘的侧壁。

公开(公告)号：US07566906B2

公开(公告)日：2009-07-28

申请号：US11958230

申请日：2007-12-17

申请人： Min-Wook Park ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  San-Jin Jeon

发明人： Min-Wook Park ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  San-Jin Jeon

IPC分类号： H01L29/04

CPC分类号： H01L29/41733 ,  H01L27/124

摘要： A thin film transistor array panel is provided, which includes a substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer; a plurality of ohmic contacts formed on the semiconductor layer; source and drain electrodes formed on the ohmic contacts; a passivation layer formed on the source and the drain electrodes and having a first contact hole exposing a portion of the drain electrode and an opening exposing a first portion of the semiconductor layer and having edges that coincide with edges of the source and the drain electrodes; and a pixel electrode formed on the passivation layer and contacting the drain electrode through the first contact hole.

摘要翻译： 提供薄膜晶体管阵列面板，其包括基板; 形成在所述基板上并包括栅电极的栅极线; 栅极绝缘层，形成在栅极线上; 形成在所述栅极绝缘层上的半导体层; 形成在所述半导体层上的多个欧姆接触; 源极和漏极形成在欧姆接触上; 形成在源电极和漏电极上的钝化层，具有露出漏电极的一部分的第一接触孔和露出半导体层的第一部分并且具有与源电极和漏电极的边缘重合的边缘的开口; 以及形成在钝化层上并通过第一接触孔接触漏电极的像素电极。

公开(公告)号：US07459323B2

公开(公告)日：2008-12-02

申请号：US11512805

申请日：2006-08-30

申请人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

发明人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

IPC分类号： H01L21/00

CPC分类号： G02F1/1368 ,  G02F1/1339

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在下导电膜的第一和第二部分上形成像素电极和一对冗余电极，所述冗余电极暴露下导电膜的第二部分的一部分; 去除下导电膜的第二部分的暴露部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

公开(公告)号：US07883942B2

公开(公告)日：2011-02-08

申请号：US11875199

申请日：2007-10-19

申请人： Bum-Gee Baek ,  Kwon-Young Choi ,  Young-Joon Rhee ,  Bong-Joo Kang ,  Seung-Taek Lim ,  Hyang-Shik Kong ,  Won-Joo Kim

发明人： Bum-Gee Baek ,  Kwon-Young Choi ,  Young-Joon Rhee ,  Bong-Joo Kang ,  Seung-Taek Lim ,  Hyang-Shik Kong ,  Won-Joo Kim

IPC分类号： H01L21/00

CPC分类号： G02F1/13458 ,  G02F1/13439 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908

摘要： Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel areas is formed on the upper film. The upper film on remaining areas are wet-etched, and the lower film and the a-Si layers on the remaining areas are dry-etched along with the second portions of the photoresist. The upper film, the lower film, and the extrinsic a-Si layer on the channel areas are removed. The removal of the upper film and the lower film on the channel areas are performed by wet etching, and the first portions of the photoresist are removed after the removal of the upper film on the channel areas.

摘要翻译： 栅极线形成在基板上。 依次沉积栅极绝缘层，本征a-Si层，外部a-Si层，下部Cr膜和含Al金属的上部膜。 在上部膜上形成具有较粗的第一部分在导线区域上的光刻胶和在沟道区域上较薄的第二部分的光致抗蚀剂。 在其余区域上的上部膜被湿式蚀刻，并且其余区域上的下部膜和a-Si层与光致抗蚀剂的第二部分一起被干蚀刻。 除去沟道区上的上膜，下膜和非本征a-Si层。 通过湿蚀刻来进行通道区域上的上膜和下膜的去除，并且在去除沟道区上的上膜之后去除光致抗蚀剂的第一部分。

公开(公告)号：US07550329B2

公开(公告)日：2009-06-23

申请号：US12119707

申请日：2008-05-13

申请人： Sahng-Ik Jun ,  Jae-Hong Jeon ,  Kwon-Young Choi ,  Jeong-Young Lee

发明人： Sahng-Ik Jun ,  Jae-Hong Jeon ,  Kwon-Young Choi ,  Jeong-Young Lee

IPC分类号： H01L21/00

CPC分类号： H01L27/124 ,  H01L29/41733

摘要： A thin film transistor array panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line formed on the substrate and intersecting the first signal line; a thin film transistor including a gate electrode connected to the first signal line and having an edge substantially parallel to the first signal line, a source electrode connected to the second signal line, and a drain electrode overlapping the edge of the gate electrode; and a pixel electrode connected to the drain electrode.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：基板; 形成在所述基板上的第一信号线; 形成在所述基板上并与所述第一信号线相交的第二信号线; 薄膜晶体管，包括连接到第一信号线的栅极，并且具有基本上平行于第一信号线的边缘，连接到第二信号线的源电极和与栅电极的边缘重叠的漏电极; 以及连接到漏电极的像素电极。

公开(公告)号：US07320906B2

公开(公告)日：2008-01-22

申请号：US10922343

申请日：2004-08-19

申请人： Min-Wook Park ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  Sang-Jin Jeon

发明人： Min-Wook Park ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  Sang-Jin Jeon

IPC分类号： H01L21/84

CPC分类号： H01L29/41733 ,  H01L27/124

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

公开(公告)号：US20050104069A1

公开(公告)日：2005-05-19

申请号：US10954524

申请日：2004-09-29

申请人： Sahng-Ik Jun ,  Jae-Hong Jeon ,  Kwon-Young Choi ,  Jeong-Young Lee

发明人： Sahng-Ik Jun ,  Jae-Hong Jeon ,  Kwon-Young Choi ,  Jeong-Young Lee

IPC分类号： G02F1/1368 ,  G02F1/136 ,  G09F9/30 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/786 ,  H01L29/04

CPC分类号： H01L27/124 ,  H01L29/41733

摘要： A thin film transistor array panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line formed on the substrate and intersecting the first signal line; a thin film transistor including a gate electrode connected to the first signal line and having an edge substantially parallel to the first signal line, a source electrode connected to the second signal line, and a drain electrode overlapping the edge of the gate electrode; and a pixel electrode connected to the drain electrode.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：基板; 形成在所述基板上的第一信号线; 形成在所述基板上并与所述第一信号线相交的第二信号线; 薄膜晶体管，包括连接到第一信号线的栅极，并且具有基本上平行于第一信号线的边缘，连接到第二信号线的源电极和与栅电极的边缘重叠的漏电极; 以及连接到漏电极的像素电极。

公开(公告)号：US20080210943A1

公开(公告)日：2008-09-04

申请号：US12119707

申请日：2008-05-13

申请人： Sahng-Ik Jun ,  Jae-Hong Jeon ,  Kwon-Young Choi ,  Jeong-Young Lee

发明人： Sahng-Ik Jun ,  Jae-Hong Jeon ,  Kwon-Young Choi ,  Jeong-Young Lee

IPC分类号： H01L27/088

CPC分类号： H01L27/124 ,  H01L29/41733

摘要： A thin film transistor array panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line formed on the substrate and intersecting the first signal line; a thin film transistor including a gate electrode connected to the first signal line and having an edge substantially parallel to the first signal line, a source electrode connected to the second signal line, and a drain electrode overlapping the edge of the gate electrode; and a pixel electrode connected to the drain electrode.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：基板; 形成在所述基板上的第一信号线; 形成在所述基板上并与所述第一信号线相交的第二信号线; 薄膜晶体管，包括连接到第一信号线的栅极，并且具有基本上平行于第一信号线的边缘，连接到第二信号线的源电极和与栅电极的边缘重叠的漏电极; 以及连接到漏电极的像素电极。

公开(公告)号：US07408200B2

公开(公告)日：2008-08-05

申请号：US11612141

申请日：2006-12-18

申请人： Sahng-Ik Jun ,  Jae-Hong Jeon ,  Kwon-Young Choi ,  Jeong-Young Lee

发明人： Sahng-Ik Jun ,  Jae-Hong Jeon ,  Kwon-Young Choi ,  Jeong-Young Lee

IPC分类号： H01L33/00

CPC分类号： H01L27/124 ,  H01L29/41733

摘要： A thin film transistor array panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line formed on the substrate and intersecting the first signal line; a thin film transistor including a gate electrode connected to the first signal line and having an edge substantially parallel to the first signal line, a source electrode connected to the second signal line, and a drain electrode overlapping the edge of the gate electrode; and a pixel electrode connected to the drain electrode.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：基板; 形成在所述基板上的第一信号线; 形成在所述基板上并与所述第一信号线相交的第二信号线; 薄膜晶体管，包括连接到第一信号线的栅极，并且具有基本上平行于第一信号线的边缘，连接到第二信号线的源电极和与栅电极的边缘重叠的漏电极; 以及连接到漏电极的像素电极。