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    Method of forming self-aligned double pattern
    1.
    发明授权
    Method of forming self-aligned double pattern 有权
    形成自对准双重图案的方法

    公开(公告)号：US07531456B2

    公开(公告)日：2009-05-12

    申请号：US11602270

    申请日：2006-11-21

    申请人： Byoung-Ho Kwon ,  Se-Rah Yun ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Joon-Sang Park

    发明人： Byoung-Ho Kwon ,  Se-Rah Yun ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Joon-Sang Park

    IPC分类号： H01L21/44

    CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  Y10S438/925

    摘要： Mask patterns used for forming patterns or trenches may include first mask patterns, which may be formed by a typical photolithography process, and second mask patterns, which may be formed in a self-aligned manner between adjacent first mask patterns. A sacrificial layer may be deposited and planarized such that the tops of the first mask patterns and the second mask patterns have planar surfaces. After the planarization of the sacrificial layer, the remaining the sacrificial layer may be removed by an ashing process.

    摘要翻译： 用于形成图案或沟槽的掩模图案可以包括可以通过典型的光刻工艺形成的第一掩模图案和可以在相邻的第一掩模图案之间以自对准方式形成的第二掩模图案。 牺牲层可以沉积并平坦化，使得第一掩模图案的顶部和第二掩模图案具有平坦表面。 在牺牲层的平坦化之后，剩余的牺牲层可以通过灰化处理去除。

    Method of forming self-aligned double pattern
    2.
    发明申请
    Method of forming self-aligned double pattern 有权
    形成自对准双重图案的方法

    公开(公告)号：US20070148968A1

    公开(公告)日：2007-06-28

    申请号：US11602270

    申请日：2006-11-21

    申请人： Byoung-Ho Kwon ,  Se-Rah Yun ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Joon-Sang Park

    发明人： Byoung-Ho Kwon ,  Se-Rah Yun ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Joon-Sang Park

    IPC分类号： H01L21/44

    CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  Y10S438/925

    摘要： Mask patterns used for forming patterns or trenches may include first mask patterns, which may be formed by a typical photolithography process, and second mask patterns, which may be formed in a self-aligned manner between adjacent first mask patterns. A sacrificial layer may be deposited and planarized such that the tops of the first mask patterns and the second mask patterns have planar surfaces. After the planarization of the sacrificial layer, the remaining the sacrificial layer may be removed by an ashing process.

    摘要翻译： 用于形成图案或沟槽的掩模图案可以包括可以通过典型的光刻工艺形成的第一掩模图案和可以在相邻的第一掩模图案之间以自对准方式形成的第二掩模图案。 牺牲层可以沉积并平坦化，使得第一掩模图案的顶部和第二掩模图案具有平坦表面。 在牺牲层的平坦化之后，剩余的牺牲层可以通过灰化处理去除。

    Method of polishing a layer and method of manufacturing a semiconductor device using the same
    5.
    发明申请
    Method of polishing a layer and method of manufacturing a semiconductor device using the same 审中-公开
    抛光层的方法和使用其制造半导体器件的方法

    公开(公告)号：US20080176403A1

    公开(公告)日：2008-07-24

    申请号：US11983281

    申请日：2007-11-08

    申请人： Jun-Yong Kim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Byoung-Ho Kwon

    发明人： Jun-Yong Kim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Byoung-Ho Kwon

    IPC分类号： H01L21/306 ,  C23F1/00

    CPC分类号： H01L21/31053 ,  C09G1/02

    摘要： In a method of chemically and mechanically polishing a layer, a substrate on which the layer having stepped portions is formed is prepared. The layer is primarily chemically and mechanically polished at a temperature of about 30° C. to about 80° C. to remove the stepped portions of the layer. The layer is secondarily chemically and mechanically polished without the stepped portions at a temperature of about 5° C. to about 25° C. to form a flat layer having a desired thickness. Thus, the stepped portions may be rapidly removed in an initial period so that the method may have an improved throughput.

    摘要翻译： 在化学和机械抛光层的方法中，制备其上形成有阶梯部分的层的基底。 该层主要在约30℃至约80℃的温度下进行化学和机械抛光，以除去该层的阶梯部分。 在约5℃至约25℃的温度下，该层被二次化学和机械抛光而没有阶梯部分以形成具有期望厚度的平坦层。 因此，可以在初始阶段快速移除阶梯部分，使得该方法可以具有改进的生产量。

    Method of fabricating self-aligned contact pad using chemical mechanical polishing process
    6.
    发明授权
    Method of fabricating self-aligned contact pad using chemical mechanical polishing process 有权
    使用化学机械抛光工艺制造自对准接触垫的方法

    公开(公告)号：US07781281B2

    公开(公告)日：2010-08-24

    申请号：US12694715

    申请日：2010-01-27

    申请人： Ho-Young Kim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Joon-Sang Park

    发明人： Ho-Young Kim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Joon-Sang Park

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/76897 ,  H01L21/7684 ,  H01L27/10873 ,  H01L27/10885

    摘要： A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks. The method further includes etching the portion of the insulation layer exposed by the opening region using the first and second etching masks to form a plurality of opening holes, removing the second etching mask, forming a conductive layer filling the opening holes to cover the remaining first etching masks and performing a chemical mechanical polishing (CMP) process on the conductive layer using the capping layer as a polishing end point to remove the first etching masks such that a plurality of SAC pads separated from each other are formed that fill the opening holes.

    摘要翻译： 一种制造自对准接触焊盘（SAC）的方法包括在半导体衬底上形成导电线和覆盖层的叠层，覆盖堆叠的侧壁的间隔物和填充堆叠之间的间隙的绝缘层， 覆盖层，蚀刻覆盖层以形成镶嵌槽，用不同于覆盖层的材料形成多个第一蚀刻掩模以填充镶嵌槽而不覆盖绝缘层的顶部，以及形成第二蚀刻掩模 具有暴露一些第一蚀刻掩模的开口区域和位于第一蚀刻掩模之间的绝缘层的一部分。 该方法还包括使用第一和第二蚀刻掩模蚀刻由开口区域暴露的绝缘层的部分，以形成多个开孔，去除第二蚀刻掩模，形成填充开孔的导电层以覆盖剩余的第一 蚀刻掩模并使用覆盖层作为抛光终点在导电层上进行化学机械抛光（CMP）工艺，以去除第一蚀刻掩模，从而形成填充开孔的彼此分离的多个SAC焊盘。

    Method of fabricating self-aligned contact pad using chemical mechanical polishing process
    7.
    发明申请
    Method of fabricating self-aligned contact pad using chemical mechanical polishing process 有权
    使用化学机械抛光工艺制造自对准接触垫的方法

    公开(公告)号：US20070072407A1

    公开(公告)日：2007-03-29

    申请号：US11525490

    申请日：2006-09-23

    申请人： Ho-Young Kim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Joon-Sang Park

    发明人： Ho-Young Kim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Joon-Sang Park

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76897 ,  H01L21/7684 ,  H01L27/10873 ,  H01L27/10885

    摘要： A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks. The method further includes etching the portion of the insulation layer exposed by the opening region using the first and second etching masks to form a plurality of opening holes, removing the second etching mask, forming a conductive layer filling the opening holes to cover the remaining first etching masks and performing a chemical mechanical polishing (CMP) process on the conductive layer using the capping layer as a polishing end point to remove the first etching masks such that a plurality of SAC pads separated from each other are formed that fill the opening holes.

    摘要翻译： 一种制造自对准接触焊盘（SAC）的方法包括在半导体衬底上形成导电线和覆盖层的叠层，覆盖堆叠的侧壁的间隔物和填充堆叠之间的间隙的绝缘层， 覆盖层，蚀刻覆盖层以形成镶嵌槽，用不同于覆盖层的材料形成多个第一蚀刻掩模以填充镶嵌槽而不覆盖绝缘层的顶部，以及形成第二蚀刻掩模 具有暴露一些第一蚀刻掩模的开口区域和位于第一蚀刻掩模之间的绝缘层的一部分。 该方法还包括使用第一和第二蚀刻掩模蚀刻由开口区域暴露的绝缘层的部分，以形成多个开孔，去除第二蚀刻掩模，形成填充开孔的导电层以覆盖剩余的第一 蚀刻掩模并使用覆盖层作为抛光终点在导电层上进行化学机械抛光（CMP）工艺，以去除第一蚀刻掩模，从而形成填充开孔的彼此分离的多个SAC焊盘。

    Method of fabricating self-aligned contact pad using chemical mechanical polishing process
    8.
    发明授权
    Method of fabricating self-aligned contact pad using chemical mechanical polishing process 有权

    公开(公告)号：US07670942B2

    公开(公告)日：2010-03-02

    申请号：US11525490

    申请日：2006-09-23

    申请人： Ho-Young Kim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Joon-Sang Park

    发明人： Ho-Young Kim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Joon-Sang Park

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76897 ,  H01L21/7684 ,  H01L27/10873 ,  H01L27/10885

    摘要： A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks. The method further includes etching the portion of the insulation layer exposed by the opening region using the first and second etching masks to form a plurality of opening holes, removing the second etching mask, forming a conductive layer filling the opening holes to cover the remaining first etching masks and performing a chemical mechanical polishing (CMP) process on the conductive layer using the capping layer as a polishing end point to remove the first etching masks such that a plurality of SAC pads separated from each other are formed that fill the opening holes.

    Slurry and method for chemical-mechanical polishing
    9.
    发明申请
    Slurry and method for chemical-mechanical polishing 审中-公开
    浆料和化学机械抛光方法

    公开(公告)号：US20070145012A1

    公开(公告)日：2007-06-28

    申请号：US11542256

    申请日：2006-10-04

    申请人： Joon-Sang Park ,  Jong-Won Lee ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

    发明人： Joon-Sang Park ,  Jong-Won Lee ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

    IPC分类号： C09K13/00 ,  C03C15/00 ,  B44C1/22

    CPC分类号： C09K3/1463 ,  C09G1/02 ,  H01L21/3212

    摘要： Disclosed is a slurry and method for chemical-mechanical polishing operation. The slurry may contain abrasive particles, an oxidizer, a pH controller, a chelating agent and water. The viscosity of the slurry may be in the range of about 1.0 cP—about 1.05 cP, so that the step difference may be reduced between regions with patterns and without patterns even after completing the chemical-mechanical polishing operation. A permissible rate of depth of focus (DOF) may not need to be controlled in the subsequent photolithography operation, which may enable the subsequent photolithography operation to be conducted by an optical system with relatively low DOF.

    摘要翻译： 公开了一种用于化学机械抛光操作的浆料和方法。 浆料可以含有磨料颗粒，氧化剂，pH控制剂，螯合剂和水。 浆料的粘度可以在约1.0cP-约1.05cP的范围内，使得即使在完成化学机械抛光操作之后，也可以在具有图案的区域与无图案的区域之间降低阶梯差。 在随后的光刻操作中可能不需要控制焦深（DOF）的允许率，这可以使得随后的光刻操作能够由具有相对低的DOF的光学系统进行。

    Methods of manufacturing semiconductors using dummy patterns
    10.
    发明授权
    Methods of manufacturing semiconductors using dummy patterns 有权
    使用虚拟图案制造半导体的方法

    公开(公告)号：US08398874B2

    公开(公告)日：2013-03-19

    申请号：US12953686

    申请日：2010-11-24

    申请人： Byoung-Ho Kwon ,  Bo-Un Yoon ,  Min-Sang Kim

    发明人： Byoung-Ho Kwon ,  Bo-Un Yoon ,  Min-Sang Kim

    IPC分类号： B44C1/22 ,  H01L21/302

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31053 ,  H01L21/76819 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of manufacturing a semiconductor device is provided. A pattern layer is formed on a substrate defined to include a main pattern region and a dummy pattern region. A preliminary main pattern and a preliminary dummy pattern may be formed by patterning the pattern layer so that an upper surface area of the preliminary dummy pattern facing away from a surface of the substrate is less than an entire area of the dummy pattern region that is be subjected to subsequent planarization. The preliminary main pattern and the preliminary dummy pattern are partially etched to form a main pattern and a dummy pattern.

    摘要翻译： 提供一种制造半导体器件的方法。 在限定为包括主图案区域和虚设图案区域的基板上形成图案层。 可以通过图案化图案层来形成预备主图案和初步虚拟图案，使得预备虚拟图案的背离基板表面的上表面区域小于虚设图案区域的整个区域 进行随后的平面化。 部分蚀刻初步主图案和初步虚拟图案以形成主图案和虚拟图案。