公开(公告)号：US20050023634A1

公开(公告)日：2005-02-03

申请号：US10862336

申请日：2004-06-08

申请人： Byoung-Moon Yoon ,  Min-Jin Lee ,  Yong-Sun Ko ,  In-Seak Hwang ,  Won-Jun Lee

发明人： Byoung-Moon Yoon ,  Min-Jin Lee ,  Yong-Sun Ko ,  In-Seak Hwang ,  Won-Jun Lee

IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L21/76 ,  H01L29/00

CPC分类号： H01L21/763 ,  H01L21/76224

摘要： Provided is a method of fabricating a shallow trench isolation (STI) structure having a high aspect ratio and improved insulating properties. The exemplary method includes filling a shallow trench isolation region opening with an undoped polysilicon layer, removing an upper portion of the undoped polysilicon layer to form a second opening having a reduced aspect ratio relative to the original opening and filling the second opening with an insulating material to complete the STI structure. Additional protective layers including silicon oxide, silicon nitride and/or a capping layer may be provided on the sidewalls of the opening before depositing the undoped polysilicon.

摘要翻译： 提供一种制造具有高纵横比和改进的绝缘性能的浅沟槽隔离（STI）结构的方法。 该示例性方法包括填充具有未掺杂多晶硅层的浅沟槽隔离区开口，去除未掺杂多晶硅层的上部，以形成相对于原始开口具有减小的纵横比的第二开口，并用绝缘材料填充第二开口 完成STI结构。 在沉积未掺杂的多晶硅之前，可以在开口的侧壁上提供包括氧化硅，氮化硅和/或覆盖层的附加保护层。

公开(公告)号：US20050064674A1

公开(公告)日：2005-03-24

申请号：US10763356

申请日：2004-01-23

申请人： Won-Jun Lee ,  Byoung -Moon Yoon ,  In-Seak Hwang ,  Yong-Sun Ko

发明人： Won-Jun Lee ,  Byoung -Moon Yoon ,  In-Seak Hwang ,  Yong-Sun Ko

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/311 ,  H01L21/20 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L28/91 ,  H01L21/31111

摘要： A wafer having a dielectric layer and an electrode partially protruding from the top surface of the dielectric layer is provided. The dielectric layer is etched with a chemical solution such as LAL. Prior to etching, the protruding portion of the electrode is removed or reduced to prevent any bubbles included in the chemical solution from adhering to the electrode. Thus, the chemical solution can etch the dielectric layers without being blocked by any bubbles included in a chemical solution.

摘要翻译： 提供具有电介质层和从电介质层的顶表面部分突出的电极的晶片。 用诸如LAL的化学溶液蚀刻电介质层。 在蚀刻之前，电极的突出部分被去除或减少，以防止化学溶液中包含的任何气泡粘附到电极上。 因此，化学溶液可以蚀刻介电层而不被包含在化学溶液中的任何气泡所阻挡。

公开(公告)号：US20050026452A1

公开(公告)日：2005-02-03

申请号：US10855313

申请日：2004-05-26

申请人： Won-Jun Lee ,  Byoung-Moon Yoon ,  In-Seak Hwang ,  Yong-Sun Ko

发明人： Won-Jun Lee ,  Byoung-Moon Yoon ,  In-Seak Hwang ,  Yong-Sun Ko

IPC分类号： H01L21/02 ,  H01L21/311 ,  H01L21/8242 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L28/91 ,  H01L21/31111 ,  H01L27/10852

摘要： A wafer having a dielectric layer and an electrode partially protruding from the top surface of the dielectric layer is provided. An etchant or chemical solution is applied to the dielectric layer and bubbles in the etchant are prevented from adhering to the electrode. In one embodiment, prior to etching, the protruding portion is covered with a buffer layer to prevent bubbles in the etchant from adhering to the electrode. Thus, the etchant can etch the dielectric layers without being blocked by bubbles included therein.

摘要翻译： 提供具有电介质层和从电介质层的顶表面部分突出的电极的晶片。 将蚀刻剂或化学溶液施加到电介质层，并且防止蚀刻剂中的气泡粘附到电极上。 在一个实施例中，在蚀刻之前，突出部分被缓冲层覆盖，以防止蚀刻剂中的气泡粘附到电极上。 因此，蚀刻剂可以蚀刻电介质层而不被其中包含的气泡阻挡。

公开(公告)号：US07338610B2

公开(公告)日：2008-03-04

申请号：US10763356

申请日：2004-01-23

申请人： Won-Jun Lee ,  Byoung-Moon Yoon ,  In-Seak Hwang ,  Yong-Sun Ko

发明人： Won-Jun Lee ,  Byoung-Moon Yoon ,  In-Seak Hwang ,  Yong-Sun Ko

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L28/91 ,  H01L21/31111

摘要： A wafer having a dielectric layer and an electrode partially protruding from the top surface of the dielectric layer is provided. The dielectric layer is etched with a chemical solution such as LAL. Prior to etching, the protruding portion of the electrode is removed or reduced to prevent any bubbles included in the chemical solution from adhering to the electrode. Thus, the chemical solution can etch the dielectric layers without being blocked by any bubbles included in a chemical solution.

摘要翻译： 提供具有电介质层和从电介质层的顶表面部分突出的电极的晶片。 用诸如LAL的化学溶液蚀刻电介质层。 在蚀刻之前，电极的突出部分被去除或减少，以防止化学溶液中包含的任何气泡粘附到电极上。 因此，化学溶液可以蚀刻介电层而不被包含在化学溶液中的任何气泡所阻挡。

公开(公告)号：US20050079682A1

公开(公告)日：2005-04-14

申请号：US10961908

申请日：2004-10-08

申请人： Mi-Jin Lee ,  Won-Jun Lee ,  In-Seak Hwang ,  Byoung-Moon Yoon

发明人： Mi-Jin Lee ,  Won-Jun Lee ,  In-Seak Hwang ,  Byoung-Moon Yoon

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76232

摘要： Provided is a method of manufacturing a shallow trench isolation (STI) film without voids or added processes. In one embodiment, the method of manufacturing an STI film includes forming a pad oxide pattern film and a silicon nitride film pattern, which define an isolation region, on a semiconductor substrate, and forming a trench by etching the semiconductor substrate to a predetermined depth using the pad oxide film pattern and the silicon nitride film pattern as masks. The resultant semiconductor substrate having the trench may be then dipped in a chemical solution containing ozone to pullback side walls of the silicon nitride film pattern. Afterward, the STI film can be formed by filling the trench with an insulating film.

摘要翻译： 提供了一种制造没有空隙或附加工艺的浅沟槽隔离（STI）膜的方法。 在一个实施例中，制造STI膜的方法包括在半导体衬底上形成限定隔离区的衬垫氧化物图案膜和氮化硅膜图案，并且通过使用以下方式将半导体衬底蚀刻到预定深度来形成沟槽 衬垫氧化膜图案和氮化硅膜图案作为掩模。 然后将具有沟槽的所得半导体衬底浸入含有臭氧的化学溶液中以拉回氮化硅膜图案的侧壁。 之后，可以通过用绝缘膜填充沟槽来形成STI膜。

公开(公告)号：US07445997B2

公开(公告)日：2008-11-04

申请号：US11103069

申请日：2005-04-11

申请人： Won-Jun Lee ,  Tae-Hyun Kim ,  Yong-Sun Ko ,  Kyung-Hyun Kim ,  Byoung-Moon Yoon ,  Ji-Hong Kim

发明人： Won-Jun Lee ,  Tae-Hyun Kim ,  Yong-Sun Ko ,  Kyung-Hyun Kim ,  Byoung-Moon Yoon ,  Ji-Hong Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： Methods of forming non-volatile memory devices include the steps of forming a semiconductor substrate having first and second floating gate electrodes thereon and an electrically insulating region extending between the first and second floating gate electrodes. A step is then performed to etch back the electrically insulating region to expose upper corners of the first and second floating gate electrodes. Another etching step is then performed. This etching step includes exposing upper surfaces and the exposed upper corners of the first and second floating gate electrodes to an etchant that rounds the exposed upper corners of the first and second floating gate electrodes. The step of etching back the electrically insulating region includes etching back the electrically insulating region to expose sidewalls of the first and second floating gate electrodes having heights ranging from about 30 Å to about 200 Å. The step of exposing the upper corners of the first and second floating gate electrodes to an etchant is followed by the step of etching back the electrically insulating region to expose entire sidewalls of the first and second floating gate electrodes.

摘要翻译： 形成非易失性存储器件的方法包括以下步骤：在其上形成具有第一和第二浮栅的半导体衬底和在第一和第二浮栅之间延伸的电绝缘区。 然后执行步骤以回蚀电绝缘区域以暴露第一和第二浮栅电极的上角。 然后执行另一蚀刻步骤。 该蚀刻步骤包括将第一和第二浮栅电极的上表面和暴露的上角露出到蚀刻剂，该蚀刻剂围绕第一和第二浮栅的暴露的上角。 蚀刻回电绝缘区域的步骤包括蚀刻电绝缘区域以暴露第一和第二浮栅电极的侧壁，其高度范围为约至约200。 将第一和第二浮栅的上角暴露于蚀刻剂的步骤之后是蚀刻电绝缘区以暴露第一和第二浮栅的整个侧壁的步骤。

公开(公告)号：US20050255654A1

公开(公告)日：2005-11-17

申请号：US11103069

申请日：2005-04-11

申请人： Won-Jun Lee ,  Tae-Hyun Kim ,  Yong-Sun Ko ,  Kyung-Hyun Kim ,  Byoung-Moon Yoon ,  Ji-Hong Kim

发明人： Won-Jun Lee ,  Tae-Hyun Kim ,  Yong-Sun Ko ,  Kyung-Hyun Kim ,  Byoung-Moon Yoon ,  Ji-Hong Kim

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： Methods of forming non-volatile memory devices include the steps of forming a semiconductor substrate having first and second floating gate electrodes thereon and an electrically insulating region extending between the first and second floating gate electrodes. A step is then performed to etch back the electrically insulating region to expose upper corners of the first and second floating gate electrodes. Another etching step is then performed. This etching step includes exposing upper surfaces and the exposed upper corners of the first and second floating gate electrodes to an etchant that rounds the exposed upper corners of the first and second floating gate electrodes. The step of etching back the electrically insulating region includes etching back the electrically insulating region to expose sidewalls of the first and second floating gate electrodes having heights ranging from about 30 Å to about 200 Å. The step of exposing the upper corners of the first and second floating gate electrodes to an etchant is followed by the step of etching back the electrically insulating region to expose entire sidewalls of the first and second floating gate electrodes.

摘要翻译： 形成非易失性存储器件的方法包括以下步骤：在其上形成具有第一和第二浮栅的半导体衬底和在第一和第二浮栅之间延伸的电绝缘区。 然后执行步骤以回蚀电绝缘区域以暴露第一和第二浮栅电极的上角。 然后执行另一蚀刻步骤。 该蚀刻步骤包括将第一和第二浮栅电极的上表面和暴露的上角露出到蚀刻剂，该蚀刻剂围绕第一和第二浮栅的暴露的上角。 蚀刻回电绝缘区域的步骤包括蚀刻电绝缘区域以暴露第一和第二浮栅电极的侧壁，其高度范围为约至约200。 将第一和第二浮栅的上角暴露于蚀刻剂的步骤之后是蚀刻电绝缘区以暴露第一和第二浮栅的整个侧壁的步骤。

公开(公告)号：US06943081B2

公开(公告)日：2005-09-13

申请号：US10445426

申请日：2003-05-27

申请人： Won-Jun Lee ,  In-Seak Hwang ,  Ji-Chul Shin

发明人： Won-Jun Lee ,  In-Seak Hwang ,  Ji-Chul Shin

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/10855 ,  H01L27/10814 ,  H01L28/91

摘要： Methods of forming an electronic structure can include forming an interlayer insulating layer on a substrate, and forming a storage node comprising a base and sidewalls extending away from the base. The interlayer insulating layer can have a contact hole therein exposing a portion of the substrate. Moreover, the storage node base can be in the contact hole and the sidewalls can extend away from the base and away from the substrate with portions of the sidewalls being within the contact hole and with portions of the sidewalls extending outside the contact hole beyond the interlayer insulating layer away from the substrate. Related structures are also discussed.

摘要翻译： 形成电子结构的方法可以包括在基板上形成层间绝缘层，以及形成包括基底和远离基底延伸的侧壁的存储节点。 层间绝缘层可以具有暴露一部分基板的接触孔。 此外，存储节点基座可以在接触孔中，并且侧壁可以远离基部延伸并远离基板，其中侧壁的一部分在接触孔内并且侧壁的部分延伸到接触孔的外部超过中间层 绝缘层远离基板。 还讨论了相关结构。

公开(公告)号：US07582559B2

公开(公告)日：2009-09-01

申请号：US11249515

申请日：2005-10-14

申请人： In-Joon Yeo ,  Won-Jun Lee ,  Tae-Hyun Kim ,  Ji-Hong Kim ,  Byoung-Moon Yoon

发明人： In-Joon Yeo ,  Won-Jun Lee ,  Tae-Hyun Kim ,  Ji-Hong Kim ,  Byoung-Moon Yoon

IPC分类号： H01L21/4763

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of manufacturing a semiconductor device includes forming an insulation pattern over a substrate. The insulation pattern has at least one opening that exposes a surface of the substrate. Then, a first polysilicon layer is formed over the substrates such that the first polysilicon layer fills the opening. The first polysilicon layer also includes a void therein. An upper portion of the first polysilicon layer is removed such that void expands to a recess and the recess is exposed. A second polysilicon layer is formed over the substrate such that the second polysilicon layer fills the recess.

摘要翻译： 制造半导体器件的方法包括在衬底上形成绝缘图案。 绝缘图案具有暴露基板表面的至少一个开口。 然后，在基板上形成第一多晶硅层，使得第一多晶硅层填充开口。 第一多晶硅层还包括空隙。 去除第一多晶硅层的上部，使得空隙膨胀到凹部并且凹部暴露。 第二多晶硅层形成在衬底上，使得第二多晶硅层填充凹部。

公开(公告)号：US20110136290A1

公开(公告)日：2011-06-09

申请号：US12959995

申请日：2010-12-03

申请人： Ki-Hyung KO ,  Byoung-Moon Yoon ,  Won-Jun Lee ,  Joon-Sang Park ,  Jun-Youl Yang ,  Seung-Ho Park ,  Myung-Jung Pyo

发明人： Ki-Hyung KO ,  Byoung-Moon Yoon ,  Won-Jun Lee ,  Joon-Sang Park ,  Jun-Youl Yang ,  Seung-Ho Park ,  Myung-Jung Pyo

IPC分类号： H01L21/306 ,  H01L21/20

CPC分类号： H01L27/14689 ,  H01L27/1464 ,  H01L27/14685

摘要： In an etching method, a thin layer is formed on a first surface of a first substrate doped with first impurities having a first doping concentration. The thin layer is doped with second impurities having a second doping concentration lower than the first doping concentration. A second substrate is formed on the thin layer. A second surface of the first substrate is polished. The polished first substrate is cleaned using a cleaning solution including ammonia and deionized water. The cleaned first substrate is etched to expose the thin layer.

摘要翻译： 在蚀刻方法中，在掺杂有具有第一掺杂浓度的第一杂质的第一衬底的第一表面上形成薄层。 该薄层掺杂有具有低于第一掺杂浓度的第二掺杂浓度的第二杂质。 第二衬底形成在薄层上。 抛光第一衬底的第二表面。 使用包括氨和去离子水的清洁溶液清洁抛光的第一衬底。 蚀刻清洁的第一衬底以暴露薄层。