公开(公告)号：US20120056295A1

公开(公告)日：2012-03-08

申请号：US13294945

申请日：2011-11-11

申请人： CHIH-PING LIN ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang

发明人： CHIH-PING LIN ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang

IPC分类号： H01L27/06

CPC分类号： H01L21/823481 ,  H01L21/823412 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892

摘要： A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.

摘要翻译： 提供一种制造半导体器件的方法。 提供了包括P阱的衬底。 在P井中定义了低压装置区域和高压装置区域。 在基板上形成光致抗蚀剂层。 提供了包括屏蔽区域的光掩模。 屏蔽区域对应于高电压设备区域。 通过使用光掩模的光刻工艺将光掩模的图案转移到基板上的光致抗蚀剂层。 通过使用光致抗蚀剂层作为掩模，通过将P型离子选择性地掺杂到衬底中，在高电压器件区域的外部形成P型离子场。

公开(公告)号：US20090236665A1

公开(公告)日：2009-09-24

申请号：US12177766

申请日：2008-07-22

申请人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang ,  Ya-Sheng Liu

发明人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang ,  Ya-Sheng Liu

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/027

CPC分类号： H01L29/7836 ,  H01L29/0653

摘要： A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括半导体衬底，其包括第一类型阱和第二类型阱以及它们之间的多个结区域，其中每个连接区域邻接第一和第二类型阱。 栅电极，设置在半导体衬底上并覆盖至少两个接合区域。 源极和漏极在与栅电极相对的半导体衬底中。

公开(公告)号：US09219012B2

公开(公告)日：2015-12-22

申请号：US13294945

申请日：2011-11-11

申请人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang

发明人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang

IPC分类号： H01L29/00 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/823481 ,  H01L21/823412 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892

摘要： A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.

摘要翻译： 提供一种制造半导体器件的方法。 提供了包括P阱的衬底。 在P井中定义了低压装置区域和高压装置区域。 在基板上形成光致抗蚀剂层。 提供了包括屏蔽区域的光掩模。 屏蔽区域对应于高电压设备区域。 通过使用光掩模的光刻工艺将光掩模的图案转移到基板上的光致抗蚀剂层。 通过使用光致抗蚀剂层作为掩模，通过将P型离子选择性地掺杂到衬底中，在高电压器件区域的外部形成P型离子场。

公开(公告)号：US20110062500A1

公开(公告)日：2011-03-17

申请号：US12953347

申请日：2010-11-23

申请人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang ,  Ya-Sheng Liu

发明人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang ,  Ya-Sheng Liu

IPC分类号： H01L29/80

CPC分类号： H01L29/7836 ,  H01L29/0653

摘要： A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括半导体衬底，其包括第一类型阱和第二类型阱以及它们之间的多个结区域，其中每个连接区域邻接第一和第二类型阱。 栅电极，设置在半导体衬底上并覆盖至少两个接合区域。 源极和漏极在与栅电极相对的半导体衬底中。

公开(公告)号：US20090236681A1

公开(公告)日：2009-09-24

申请号：US12177779

申请日：2008-07-22

申请人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang

发明人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang

IPC分类号： H01L29/00 ,  H01L21/76

CPC分类号： H01L21/823481 ,  H01L21/823412 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892

摘要： A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.

摘要翻译： 提供一种制造半导体器件的方法。 提供了包括P阱的衬底。 在P井中定义了低压装置区域和高压装置区域。 在基板上形成光致抗蚀剂层。 提供了包括屏蔽区域的光掩模。 屏蔽区域对应于高电压设备区域。 通过使用光掩模的光刻工艺将光掩模的图案转移到基板上的光致抗蚀剂层。 通过使用光致抗蚀剂层作为掩模，通过将P型离子选择性地掺杂到衬底中，在高电压器件区域的外部形成P型离子场。

公开(公告)号：US08080455B2

公开(公告)日：2011-12-20

申请号：US12177779

申请日：2008-07-22

申请人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang

发明人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823481 ,  H01L21/823412 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892

摘要： A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.

摘要翻译： 提供一种制造半导体器件的方法。 提供了包括P阱的衬底。 在P井中定义了低压装置区域和高压装置区域。 在基板上形成光致抗蚀剂层。 提供了包括屏蔽区域的光掩模。 屏蔽区域对应于高电压设备区域。 通过使用光掩模的光刻工艺将光掩模的图案转移到基板上的光致抗蚀剂层。 通过使用光致抗蚀剂层作为掩模，通过将P型离子选择性地掺杂到衬底中，在高电压器件区域的外部形成P型离子场。

公开(公告)号：US08063439B2

公开(公告)日：2011-11-22

申请号：US12953347

申请日：2010-11-23

申请人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang ,  Ya-Sheng Liu

发明人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang ,  Ya-Sheng Liu

IPC分类号： H01L29/80

CPC分类号： H01L29/7836 ,  H01L29/0653

摘要： A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.

公开(公告)号：US07863147B2

公开(公告)日：2011-01-04

申请号：US12177766

申请日：2008-07-22

申请人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang ,  Ya-Sheng Liu

发明人： Chih-Ping Lin ,  Pi-Kuang Chuang ,  Hung-Li Chang ,  Shih-Ming Chen ,  Hsiao-Ying Yang ,  Ya-Sheng Liu

IPC分类号： H01L21/00

CPC分类号： H01L29/7836 ,  H01L29/0653

摘要： A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括半导体衬底，其包括第一类型阱和第二类型阱以及它们之间的多个结区域，其中每个连接区域邻接第一和第二类型阱。 栅电极，设置在半导体衬底上并覆盖至少两个接合区域。 源极和漏极在与栅电极相对的半导体衬底中。

公开(公告)号：US20080067638A1

公开(公告)日：2008-03-20

申请号：US11522446

申请日：2006-09-18

申请人： Hung-Li Chang ,  Jack C. Huang ,  Clement Ho

发明人： Hung-Li Chang ,  Jack C. Huang ,  Clement Ho

IPC分类号： H01L23/495

CPC分类号： H01L23/4951 ,  H01L2224/4826 ,  H01L2224/49171

摘要： A chip-scale packaging leadframe for a memory chip is provided, where the external leads of at least a pair of the VDD leads and at least a pair of the VSS leads are arranged on two parallel and opposing sides, namely, the first side and the third side, respectively, while all or almost all external leads of the other leads are arranged on the other two parallel and opposing sides, namely, the second side and the fourth side, respectively. According to the present invention, the dimension of the external leads of the VDD and VSS leads should be at least 0.4×1.15 mm; or the area of the external leads of the VDD and VSS leads should be at least 1.8 times of that of the other leads. Also according to the present invention, the gap of the external leads of adjacent VDD and VSS leads should be at least 1.0 mm; or at least two times of that of the other leads.

摘要翻译： 提供了一种用于存储器芯片的芯片级封装引线框架，其中至少一对V DD引线的外部引线和至少一对V SS SS引脚， 引线分别布置在两个平行和相对的侧面上，即第一侧和第三侧，而其他引线的所有或几乎所有外部引线布置在另外两个平行和相对的侧面上，即第二侧和 第四方面。 根据本发明，V DD和SS SS引线的外部引线的尺寸应至少为0.4×11.5mm; 或者V DD和SS SS引线的外部引线的面积应至少为其他引线的1.8倍。 同样根据本发明，相邻的V DD和V SS引线的外部引线的间隙应至少为1.0mm; 或至少是其他引线的两倍。

公开(公告)号：US20200375069A1

公开(公告)日：2020-11-26

申请号：US16391250

申请日：2019-04-22

申请人： Yoatian Zhang ,  George R. Woody ,  Hung-Li Chang ,  Paul F. Carosa ,  Ramiro R. Montalvo

发明人： Yoatian Zhang ,  George R. Woody ,  Hung-Li Chang ,  Paul F. Carosa ,  Ramiro R. Montalvo

IPC分类号： H05K7/20 ,  H01L25/07

摘要： An improved power semiconductor heat dissipation apparatus for regulating the temperature of multiple power semiconductors featuring increased structural integrity for high pressure applications, a more robust heat exchange fin design to accommodate particulates or other solid contaminants that may be present in less refined coolant fluids, and a modified construction for increased durability and ease of automated assembly.