公开(公告)号：US10115637B2

公开(公告)日：2018-10-30

申请号：US15820811

申请日：2017-11-22

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Claire Fenouillet-Beranger ,  Benoit Mathieu ,  Philippe Coronel

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/8232 ,  H01L21/822 ,  H01L21/324 ,  H01L21/268 ,  H01L27/02 ,  H01L21/306 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/8238 ,  H01L21/027 ,  H01L27/06

摘要： Method for fabricating transistors for an integrated 3D circuit, comprising: a) forming, on a given level of transistors made in a first semiconductor layer: a stack comprising a first region of a second semiconductor zone suitable for an N-type transistor channel and a second region of the second semiconductor zone suitable for a P-type transistor channel of a higher level, the stack moreover comprising a ground plane continuous layer (40), as well as an insulating layer between the ground plane and the second semiconductor layer, then b) exposing source and drain zones of the circuit to a laser (L), so as to carry out at least one thermal activation annealing, where the exposed source and drain zones are located next to an upper surface of the ground plane continuous layer, where the ground plane continuous layer is configured so as to protect at least a part of the circuit located on the side of a lower face of the ground plane continuous layer from the laser, then c) carrying out cutting up of the ground plane continuous layer (40) into at least one first portion and one second portion separated from the first portion, where the first portion is configured to allow biasing of the first region, where the second portion is configured to allow biasing of the second region.

公开(公告)号：US09853130B2

公开(公告)日：2017-12-26

申请号：US15049468

申请日：2016-02-22

申请人： Commissariat a L'Energie Atomique et aux Energies Alternatives

发明人： Sylvain Maitrejean ,  Emmanuel Augendre ,  Jean-Charles Barbe ,  Benoit Mathieu ,  Yves Morand

IPC分类号： H01L21/469 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/311 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L29/6681 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/31144 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/78696

摘要： A method of modifying a strain state of a first channel structure in a transistor is provided, said structure being formed from superposed semiconducting elements, the method including providing on a substrate at least one first semiconducting structure formed from a semiconducting stack including alternating elements based on at least one first semiconducting material and elements based on at least one second semiconducting material different from the first material; then removing portions of the second material from the first semiconducting structure by selective etching, the removed portions forming at least one empty space; filling the empty space with a dielectric material; forming a straining zone on the first semiconducting structure based on a first strained material having an intrinsic strain; and performing thermal annealing to cause the dielectric material to creep, and to cause a change in a strain state of the elements based on the first material.

公开(公告)号：US10586740B2

公开(公告)日：2020-03-10

申请号：US16191951

申请日：2018-11-15

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Benoit Mathieu ,  Perrine Batude

IPC分类号： H01L21/82 ,  H01L21/8238 ,  H01L21/822 ,  H01L27/092 ,  H01L21/033 ,  H01L29/66 ,  H01L29/04 ,  H01L21/266

摘要： Method for producing a device provided with FinFET transistors, comprising the following steps: a) making amorphous and doping a first portion of a semiconductor in via a tilted beam oriented toward a first lateral face of the fin, while retaining a first crystalline semiconductor block against a second lateral face of the fin, then b) carrying out at least one recrystallization annealing of said first portion, then c) making amorphous and doping a second portion via a tilted beam oriented toward the second lateral face of the fin, while retaining a second crystalline semiconductor block against said first lateral face of the fin, then d) carrying out at least one recrystallization annealing of the second portion.

公开(公告)号：US10147818B2

公开(公告)日：2018-12-04

申请号：US14950416

申请日：2015-11-24

申请人： Commissariat A L'Energie Atomique et aux Energies Alternatives

发明人： Shay Reboh ,  Benoit Mathieu

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/51

摘要： A method of straining a transistor channel zone is provided, including a) forming a plurality of stress blocks based on a material having an intrinsic stress, around a zone based on a semiconducting material in which a transistor channel will be made and on which a transistor gate will be formed, the stress blocks inducing a stress in the zone; b) forming a gate block on the zone, the gate block being disposed between the stress blocks; and c) at least partially removing the stress blocks without removing the gate block, wherein the gate block has a Young's modulus and a thickness such that the stress blocks are at least partially removed in step c) and the induced stress is at least partially maintained in the zone after the stress blocks are at least partially removed.