3D CIRCUIT WITH N AND P JUNCTIONLESS TRANSISTORS

    公开(公告)号:US20190148367A1

    公开(公告)日:2019-05-16

    申请号:US16184346

    申请日:2018-11-08

    摘要: Production of an integrated circuit provided with several superposed levels of transistors, comprising: providing a structure provided with transistors of a lower level covered by an insulating layer itself covered by a stack with a first doped semi-conducting layer according to a doping of a first type, and a second doped semi-conducting layer according to a doping of opposite type, the first doped semi-conducting layer and the second doped semi-conducting layer being superposed and in contact with one another, etching the stack so as to form, on the insulating layer, a first block and a second block, then, removing in a given zone of the second block, the second given doped semi-conducting layer, forming a first gate on the second doped semi-conducting layer of the first block and a second gate on the first doped semi-conducting layer of the second block.

    Transistor with controlled overlap of access regions

    公开(公告)号:US10553702B2

    公开(公告)日:2020-02-04

    申请号:US15485246

    申请日:2017-04-12

    摘要: A method for producing a microelectronic device with one or more transistor(s) including forming a first gate on a region of a semiconductor layer, forming a first cavity in the semiconductor layer, the first cavity having a wall contiguous with the given region, filling the first cavity in such a way as to form a first semiconductor block wherein a source or drain region of the first transistor is capable of being produced, by epitaxial growth of a first semiconductor material in the first cavity, the growth being carried out such that a first zone of predetermined thickness of the layer of first semiconductor material lines the wall contiguous with the given region, epitaxial growth of a second zone made of a second semiconductor material on the first zone.

    Method for manufacturing a transistor in which the strain applied to the channel is increased
    6.
    发明授权
    Method for manufacturing a transistor in which the strain applied to the channel is increased 有权
    制造施加到通道的应变的晶体管的制造方法

    公开(公告)号:US09343375B2

    公开(公告)日:2016-05-17

    申请号:US14802283

    申请日:2015-07-17

    摘要: Method of manufacturing a transistor on a layer made of a first crystalline semiconducting material to make a channel, deposited on a dielectric layer, the method including the following steps: epitaxial growth of zones made of a second semiconducting material on the layer made of a first crystalline semiconducting material, so as to form source and drain blocks with the layer made of a first crystalline semiconducting material on each side of the channel, the second semiconducting material having a lattice parameter different from that of the first semiconducting material, in-depth amorphization of part of zones made of a second semiconducting material so as to keep only one layer of second crystalline semiconducting material on the surface of the source and drain blocks, and amorphization of zones of the layer made of a first semiconducting material located under zones made of a second semiconducting material, recrystallization of the source and drain blocks such that the second semiconducting material imposes its lattice parameter on the source and drain zones.

    摘要翻译: 在由第一晶体半导体材料制成的层上制造沉积在电介质层上的沟道的晶体管的方法,所述方法包括以下步骤:由第二半导体材料制成的区域在第一 晶体半导体材料,以便在通道的每一侧上由第一晶体半导体材料制成的层形成源极和漏极区段,第二半导体材料具有不同于第一半导体材料的晶格参数,深度非晶化 的部分由第二半导体材料制成的区域,以便在源极和漏极区域的表面上仅保持一层第二晶体半导体材料,以及由位于由第一半导体材料制成的区域下方的第一半导体材料制成的层的区域的非晶化 第二半导体材料,源极和漏极块的再结晶,使得第二半导体材料 导电材料在源极和漏极区域施加其晶格参数。

    METHOD FOR FORMING A VIA CONTACTING SEVERAL LEVELS OF SEMICONDUCTOR LAYERS
    7.
    发明申请
    METHOD FOR FORMING A VIA CONTACTING SEVERAL LEVELS OF SEMICONDUCTOR LAYERS 有权
    形成通过接触半导体层的几个层次的方法

    公开(公告)号:US20130196500A1

    公开(公告)日:2013-08-01

    申请号:US13748126

    申请日:2013-01-23

    IPC分类号: H01L21/768

    摘要: A method for forming a via connecting a first upper level layer to a second lower level layer, both layers being surrounded with an insulating material, the method including the steps of: a) forming an opening to reach an edge of the first layer, the opening laterally continuing beyond said edge; b) forming a layer of a protection material on said edge only; c) deepening said opening by selectively etching the insulating material to reach the second lower level layer; and d) filling the opening with at least one conductive contact material.

    摘要翻译: 一种用于形成连接第一上层与第二下层的通孔的方法,所述两层被绝缘材料包围,所述方法包括以下步骤:a)形成开口以到达第一层的边缘, 横向延伸超过所述边缘; b)仅在所述边缘上形成保护材料层; c)通过选择性地蚀刻绝缘材料到达第二较低层来加深所述开口; 以及d)用至少一个导电接触材料填充该开口。