公开(公告)号：US12233577B2

公开(公告)日：2025-02-25

申请号：US18693438

申请日：2022-09-22

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Hubert Teyssedre ,  Nicolas Posseme ,  Stefan Landis

IPC: B29C33/38 ,  B29C59/02

Abstract: A method for manufacturing a mould for nanoprinting and the associated mould, includes providing a substrate having a layer, and at least one ion implantation configured so as to obtain in the layer, at least one first non-implanted portion or portion having a first implantation, at least one second portion having a second implantation, and a third non-implanted portion distinct from the first portion. After implantation, the method includes etching the layer configured so as to have a different etching speed between at least the second portion and the third portion, so as to etch through the openings of an etching mask, a plurality of patterns of different heights being included in the layer.

公开(公告)号：US11387147B2

公开(公告)日：2022-07-12

申请号：US16988892

申请日：2020-08-10

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas Posseme ,  Cyrille Le Royer ,  Fabrice Nemouchi

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

Abstract: A method is provided for producing a component based on a plurality of transistors on a substrate including an active area and an electrical isolation area, each transistor including a gate and spacers on either side of the gate, the electrical isolation area including at least one cavity formed as a hollow between a spacer of a first transistor of the plurality of transistors and a spacer of a second transistor of the plurality of transistors, the first and the second transistors being adjacent, the method including: forming the gates of the transistors; forming the spacers; and forming a mechanically constraining layer for the transistors; and after forming the spacers and before forming the mechanically constraining layer, forming a filling configured to at least partially fill, with a filling material, the at least one cavity within the electrical isolation area, between the spacers of the first and the second transistors.

公开(公告)号：US11244868B2

公开(公告)日：2022-02-08

申请号：US16999642

申请日：2020-08-21

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas Posseme

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/306 ,  H01L21/762

Abstract: A method for producing a component is provided, a base of which is formed by transistors on a substrate, including: forming a gate area, spacers, and a protective coating partly covering the spacers and a sidewall portion of a cavity without covering a top face of the gate area and a base portion of the cavity; forming a contact module, the gate located in beneath the module; and removing part of the coating with an isotropic light-ion implantation to form modified superficial parts in a thickness, respectively, of the contact module, of the coating, and of the base portion, and with an application of a plasma to: etch the modified superficial parts to only preserve, in the coating, a residual part of the coating, and to form a silicon oxide-based film on exposed surfaces, respectively, of the contact module, of the cavity, and of the coating.

公开(公告)号：US11227936B2

公开(公告)日：2022-01-18

申请号：US16722246

申请日：2019-12-20

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas Posseme

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3115 ,  H01L29/08 ,  H01L29/49

Abstract: There is provided a method for producing a transistor with a raised source and drain the method including depositing a layer on the gate pattern and the active layer; carrying out an isotropic modification of the layer over a thickness to obtain a first portion of modified layer, carrying out an anisotropic modification of the layer over another thickness, along a direction normal to the active layer, to obtain second portions of modified layer, by conserving portions of non-modified layer on the flanks of the gate pattern and at the foot of the gate pattern, removing the first and second modified portions by conserving the portions, by selective etching, to form spacers having an L-shape, epitaxially growing the source and drain in contact with the L-shaped spacers, to obtain the source and drain having tilted faces.

公开(公告)号：US10056470B2

公开(公告)日：2018-08-21

申请号：US15408793

申请日：2017-01-18

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Christian Arvet ,  Nicolas Posseme

IPC: H01L21/302 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L29/66636 ,  H01L21/02238 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76831 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78696

Abstract: A method for manufacturing a transistor is provided, the transistor including a gate disposed above an underlying layer of a semiconductor material, the gate including at least one first flank and at least one second flank, and a gate foot disposed under the gate in the underlying layer and protruding relative to a peripheral portion of the underlying layer, the peripheral portion surrounding the gate foot; and the method including forming a selectivity layer obtained from an original layer and disposed only above the peripheral portion of the underlying layer, and selective etching, with respect to the selectivity layer, of the material of the original layer so as to etch the gate foot.

公开(公告)号：US10014386B2

公开(公告)日：2018-07-03

申请号：US15408571

申请日：2017-01-18

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Nicolas Posseme ,  Christian Arvet

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/6653 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7838 ,  H01L29/78618 ,  H01L29/78654

Abstract: There is provided a method for manufacturing a transistor including a gate above an underlying layer of a semiconductor material and including at least one first flank and one second flank, a gate foot formed in the underlying layer, a peripheral portion of the underlying layer surrounding the gate foot, and spacers covering at least partially the first and second flanks so as to not cover the gate foot; the method including forming the underlying layer by partially removing the semiconductor material around the gate to form the gate foot and the peripheral portion; then forming a dielectric layer for forming spacers by a deposition to cover both the first and second flanks, the gate foot, and an upper surface of the peripheral portion; and then partially removing the dielectric layer so as to expose the upper surface and so as to not expose the first and second flanks.

公开(公告)号：US09679802B2

公开(公告)日：2017-06-13

申请号：US14661371

申请日：2015-03-18

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas Posseme

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76802 ,  H01L21/02126 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831

Abstract: A method for producing interconnection lines including etching a layer of porous dielectric material forming a trench and filling the trench is provided. The etching is carried out in a plasma so as to grow, all along the etching, a protective layer on flanks of the layer of porous dielectric material. The plasma is formed from a gas formed from a first component and a second component, or a gas formed from a first component, a second component and a third component. The first component is a hydrocarbon of the CXHY type, where X is the proportion of carbon in the gas and Y the proportion of hydrogen in the gas; the second component is taken from nitrogen or dioxygen or a mixture of nitrogen and dioxygen; the third component is taken from argon or helium; and the protective layer is based on hydrocarbon.

公开(公告)号：US09484217B2

公开(公告)日：2016-11-01

申请号：US14797325

申请日：2015-07-13

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Nicolas Posseme

IPC: H01L21/311 ,  H01L21/768 ,  H01L29/16 ,  H01L21/033 ,  H01L29/66 ,  H01L29/161 ,  H01L21/265 ,  H01L21/02 ,  H01L21/3115 ,  H01L29/417

CPC classification number: H01L21/31105 ,  H01L21/02063 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/2236 ,  H01L21/2658 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/31155 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76897 ,  H01L29/16 ,  H01L29/161 ,  H01L29/41733 ,  H01L29/66477 ,  H01L29/66795 ,  H01L2221/1063

Abstract: A method for making contact openings for connecting a transistor from a stack of layers comprising an active layer made of a semi-conductor material, a silicide layer on the top of the active layer, a nitride-based layer on the top of the silicide layer, and an electrically insulating layer on the top of the nitride-based layer, includes opening for forming, in the insulating layer, an exposing opening on the nitride-based layer and delimited by flanks of the insulating layer, and removing the nitride-based layer by modifying the nitride-based layer at the opening using plasma wherein CxHy is introduced where x is the proportion of carbon and y is the proportion of hydrogen ions and comprising ions heavier than hydrogen. The conditions of plasma being so chosen as to modify a portion of the nitride-based layer and to form a protective carbon film on the flanks of the insulating layer.

Abstract translation: 一种制造接触开口的方法，用于从包括由半导体材料制成的有源层的层叠层连接晶体管，在有源层的顶部上的硅化物层，在硅化物层的顶部上的氮化物基层 ，并且在氮化物基层的顶部上的电绝缘层包括用于在绝缘层中形成在氮化物基层上的暴露开口并由绝缘层的侧面限定的开口，并且去除氮化物基 通过使用等离子体修改开口处的氮化物层，其中引入C x H y，其中x是碳的比例，y是氢离子并且包含比氢重的离子的比例。 选择等离子体的条件来改变氮化物基层的一部分并在绝缘层的侧面上形成保护性碳膜。

公开(公告)号：US12033859B2

公开(公告)日：2024-07-09

申请号：US17652324

申请日：2022-02-24

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Valentin Bacquie ,  Nicolas Posseme

IPC: H01L21/28 ,  H01L21/3115

CPC classification number: H01L21/28123 ,  H01L21/31155

Abstract: A method is provided for forming spacers of a gate of a transistor, including: providing an active layer surmounted by a gate; forming a dielectric layer covering the gate and the active layer, the dielectric layer having lateral portions and basal portions; anisotropically modifying the basal portions by implantation of light ions, forming modified basal portions; and removing the modified basal portions by selective etching, so as to form the spacers on the lateral flanks of the gate from the unmodified lateral portions, in which, before the removing step, the anisotropic modification of the basal portions includes n successive implantation phases having implantation energies Γi (i=1 . . . n) which are distinct from each other, the n phases being configured to implant the light ions at different nominal implantation depths.

公开(公告)号：US11515148B2

公开(公告)日：2022-11-29

申请号：US16914541

申请日：2020-06-29

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Loic Gaben ,  Cyrille Le Royer ,  Fabrice Nemouchi ,  Nicolas Posseme ,  Shay Reboh

IPC: H01L21/02 ,  H01L21/8238 ,  H01L21/3105

Abstract: Method for producing a semiconductor device, including: producing, on a first region of a surface layer comprising a first semiconductor and disposed on a buried dielectric layer, a layer of a second compressive strained semiconductor along a first direction; etching a trench through the layer of the second semiconductor forming an edge of a portion of the layer of the second semiconductor oriented perpendicularly to the first direction, and wherein the bottom wall is formed by the surface layer; thermal oxidation forming in the surface layer a semiconductor compressive strained portion along the first direction and forming in the trench an oxide portion; producing, through the surface layer and/or the oxide portion, and through the buried dielectric layer, dielectric isolation portions around an assembly formed of the compressive strained semiconductor portion and the oxide portion; and wherein the first semiconductor is silicon, the second semiconductor is SiGe, and said at least one compressive strained semiconductor portion includes SiGe.