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公开(公告)号：US20240282765A1
公开(公告)日：2024-08-22
申请号：US18567101
申请日：2022-06-15
发明人： Lu HUANG , Yong HUANG , Yan YAN , Wanyi ZHOU , Lin WU , Cheng ZHOU , Haili SHI
CPC分类号： H01L27/0262 , H01L27/0274 , H01L29/7436
摘要： The present disclosure provides a GGNMOS transistor structure, an ESD protection device, and an ESD protection circuit. The GGNMOS transistor structure can increase a capability of the ESD protection device to discharge an ESD current per unit size under the action of a P-N-P-N parasitic thyristor formed by an N-potential well, a P-type heavily doped region, and an N-type heavily doped region; the GGNMOS transistor structure can limit a transient peak current of ESD under the action of an equivalent resistor formed by an N-potential well, so that respective GGNMOS transistors of the ESD protection device can conduct uniformly, improving the reliability of the ESD protection circuit.
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公开(公告)号：US20240222478A1
公开(公告)日：2024-07-04
申请号：US18558422
申请日：2022-01-24
IPC分类号： H01L29/739 , H01L27/07 , H01L29/423 , H01L29/866
CPC分类号： H01L29/7394 , H01L27/0727 , H01L29/4236 , H01L29/866
摘要： A reverse conducting lateral insulated-gate bipolar transistor includes a drift region formed on a substrate, a gate located on the drift region, an emitter region located on the drift region and close to one side of the gate, and a collector region located on the drift region and away from one side of the gate. Two or more N-well regions arranged at intervals are provided on the side of the drift region where the collector region is located. A P-well region is provided between the two or more N-well regions arranged at intervals; a P+ contact region is provided on the N-well region; an N+ contact region is provided on the P-well region; both the P+ contact region and the N+ contact region are conductively connected to a collector lead-out end.
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公开(公告)号：US12009129B2
公开(公告)日：2024-06-11
申请号：US18308399
申请日：2023-04-27
发明人： Congying Dong
IPC分类号： H01F17/00 , H01L23/522
CPC分类号： H01F17/0013 , H01L23/5227 , H01F2017/0086
摘要： A stacked spiral inductor, comprising: a substrate, and multiple stacked insulating layers and inductive metal layers formed on the substrate by means of a semiconductor process. Each inductive metal layer comprises a conductive coil in a shape of a spiral and a through hole area used for connecting two adjacent inductive metal layers. The conductive coils of the inductive metal layers have a common coil center. In two adjacent inductive metal layers, the conductive coil of the lower inductive metal layer is retracted toward the coil center with respect to the conductive coil of the upper inductive metal layer.
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公开(公告)号：US11894458B2
公开(公告)日：2024-02-06
申请号：US17762206
申请日：2020-09-25
发明人： Jiaxing Wei , Qichao Wang , Kui Xiao , Dejin Wang , Li Lu , Ling Yang , Ran Ye , Siyang Liu , Weifeng Sun , Longxing Shi
IPC分类号： H01L29/78
CPC分类号： H01L29/7825
摘要： A lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), including: a trench gate including a lower part inside a trench and an upper part outside the trench, a length of the lower part in a width direction of a conducting channel being less than that of the upper part, and the lower part extending into a body region and having a depth less than that of the body region; an insulation structure arranged between a drain region and the trench gate and extending downwards into a drift region, a depth of the insulation structure being less than that of the drift region.
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公开(公告)号：US20230036341A1
公开(公告)日：2023-02-02
申请号：US17789628
申请日：2020-09-04
发明人： Jingchuan ZHAO , Zhili ZHANG , Sen ZHANG
摘要： Disclosed are a laterally diffused metal oxide semiconductor device and a method for preparing the same. The device includes a substrate (101) of a first conductivity type, a drift region (102) of a second conductivity type, a longitudinal floating field plate array and a plurality of implantation regions (103) of the first conductivity type. The drift region is located in the substrate of the first conductivity type. The longitudinal floating field plate array includes a plurality of longitudinal floating field plate structures (104) arranged at intervals in rows and columns. Each longitudinal floating field plate structures includes a dielectric layer (1041) disposed on an inner surface of a trench and a conductive layer (1042) filling the trench. The plurality of implantation regions are located in the drift region of, each implantation region is located between two adjacent longitudinal floating field plate structures in each row.
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公开(公告)号：US11515395B2
公开(公告)日：2022-11-29
申请号：US17624336
申请日：2020-09-25
发明人： Siyang Liu , Ningbo Li , Dejin Wang , Kui Xiao , Chi Zhang , Sheng Li , Xinyi Tao , Weifeng Sun , Longxing Shi
IPC分类号： H01L29/872 , H01L29/20 , H01L29/66 , H01L21/02 , H01L29/06 , H01L29/861
摘要： A gallium nitride power device, including: a gallium nitride substrate; cathodes; a plurality of gallium nitride protruding structures arranged on the gallium nitride substrate and between the cathodes, a groove is formed between adjacent gallium nitride protruding structures; an electron transport layer, covering a top portion and side surfaces of each of the gallium nitride protruding structures; a gallium nitride layer, arranged on the electron transport layer and filling each of the grooves; a plurality of second conductivity type regions, where each of the second conductivity type regions extends downward from a top portion of the gallium nitride layer into one of the grooves, and the top portion of each of the gallium nitride protruding structures is higher than a bottom portion of each of the second conductivity type regions; and an anode, arranged on the gallium nitride layer and the second conductivity type regions.
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公开(公告)号：US20220336657A1
公开(公告)日：2022-10-20
申请号：US17620952
申请日：2020-05-26
发明人： Zhili ZHANG , Jingchuan ZHAO , Sen ZHANG
摘要： A laterally diffused metal-oxide-semiconductor (LDMOS) device and a method of manufacturing the LDMOS device are disclosed. The method includes: obtaining a substrate with a drift region formed thereon, the drift region having a first conductivity type and disposed on the substrate of a second conductivity type; etching the drift region to form therein a sinking structure, the sinking structure includes at least one of an implanting groove and an implanting hole; implanting ions of the second conductivity type at the bottom of the sinking structure; forming a buried layer of the second conductivity type by causing diffusion of the ions of the second conductivity type using a thermal treatment; and filling an electrical property modification material into the sinking structure, the electrical property modification material differs from the material of the drift region.
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公开(公告)号：US11315824B2
公开(公告)日：2022-04-26
申请号：US16483081
申请日：2018-07-03
发明人： Shukun Qi
IPC分类号： H01L21/762 , H01L21/02 , H01L21/265 , H01L21/3105 , H01L21/311 , H01L21/32 , H01L21/761 , H01L29/06
摘要： A method for manufacturing a trench isolation structure comprising forming a shallow trench having a wider upper section and a narrower lower section in a wafer surface, removing part of the silicon oxide by etching, forming a silicon oxide corner structure at a corner at a top corner of the shallow trench by thermal oxidation, depositing silicon nitride on the wafer surface to cover surfaces of the shallow trench silicon oxide and the silicon oxide corner structure, dry etching the silicon nitride on the shallow trench silicon oxide surface thereby forming masking silicon nitride residues extending into the trench, etching downwards to form a deep trench, forming silicon oxide layers on a side wall and the bottom of the deep trench, depositing polycrystalline silicon in the shallow and deep trenches, removing the silicon nitride, and forming silicon oxide in the shallow trench to cover the polycrystalline silicon.
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公开(公告)号：US11309406B2
公开(公告)日：2022-04-19
申请号：US16770362
申请日：2018-12-05
发明人： Nailong He , Sen Zhang , Guangsheng Zhang , Yun Lan
IPC分类号： H01L29/66 , H01L21/762 , H01L29/417 , H01L21/033 , H01L29/06 , H01L29/78 , H01L29/423
摘要： A manufacturing method of an LDMOS device comprises: obtaining a wafer formed with a doped region having a first conductivity type, wherein a top buried layer is formed inside the doped region having the first conductivity type, and a field oxide insulation layer structure is formed on the top buried layer; disposing a trench on the doped region having the first conductivity type, wherein the trench extends to the top buried layer and the field oxide insulation layer structure such that a portion of the top buried layer is removed; injecting an ion of a second conductivity type to form a well region below the trench; and forming a doped source region in the well region. The first conductivity type and the second conductivity type are opposite conductivity types.
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公开(公告)号：US20220077865A1
公开(公告)日：2022-03-10
申请号：US17419548
申请日：2019-12-23
摘要： An analog-to-digital converter and a clock generation circuit thereof are provided. The clock generation circuit comprises cascaded clock generation modules. The clock generation module at each stage is configured to generate a corresponding internal clock signal, and each stage of the clock generation module comprises a delay module and a logic gate module. The second input end of the N-th stage of the logic gate module is connected to the output end of the previous stage of the logic gate module, and the output end of the logic gate module is configured to output an internal clock, so that each stage of the clock generation module can generate one internal clock signal.
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